Clocking scheme for ASIC

Details Clocking scheme for ASIC Clocking scheme for ASIC

2001-06-13

2003-04-22

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S144000, C327S145000

Reexamination Certificate

active

06552590

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to application specific integrated circuits and more particularly to such circuits which require a substantial variety of clock signals at different, though related. frequencies for the operation of a multiplicity of operational blocks within the application specific integrated circuit.
BACKGROUND OF THE INVENTION
In current technology there is a marked trend towards providing an entire operating system. for example a network switch. on a single large chip supporting an application specific integrated circuit Certain features. such as keypads and terminal connectors for physical lines and large scale memories are necessarily practical exceptions.
A ‘system on a chip’ architecture customarily envisages a large number of disparate operational blocks at least some of which are predefined before design and lay-out of the integrated circuit Whether or not such blocks are taken from a ‘library’ in a practical large scale system a considerable variety of clock signals is necessary.
Although individual clock signals can be generated by high precision crystal controlled generators. minor discrepancies between nominal and actual clock frequencies can occur It is generally desirable to provide a single highly stable system clock and to provide division of that system clock to obtain the individual clock frequencies for the variety of different operational blocks within the device.
Most clocking schemes in ASICs require ‘elastic’ buffers which can cope with minor variations between clock frequencies and synchronisers to ensure smooth data transfer within the ASIC Existing schemes also require a system clock to be used by most components on the ASIC.
Routing for a system-wide system clock has in practice proved to be very difficult making timing errors a common occurrence Elastic buffers and synchronisers occupy substantial space on a silicon chip.
SUMMARY OF THE INVENTION
The invention aims to provide a clocking scheme which eliminates the need for elastic buffers and synchronisers between devices, and to reduce the need for the system clock, as such, to be used by more than a few blocks within the ASIC. so as to reduce the load on the system clock.
The present invention concerns an integrated circuit which includes a clock system wherein various clock signals (called herein simply ‘clocks’). consisting of transitions (edges) between binary values are derived from a system clock More particularly the clock system is characterised by rules which are based on the numbering of similar transitions (arbitrarily termed herein ‘positive edges’) of the system clock to distinguish between ‘even’ numbered positive edges and ‘odd’ positive edges and which prescribe the edges of the derived signals obtained by dividing the system clock Various special rules are necessary for certain types of clock to enforce the general rules.
In a preferred embodiment of the invention a high frequency system clock is provided for the ASIC. individual blocks within the ASIC dividing the system clock to generate their own clock signal The system clock can be divided by any integer to achieve an integral sub-multiple clock frequency If a block communicates with only one block at the next level of hierarchy above it, then that sub-block may generate its clock from the clock of the block above it in the hierarchy This ensures that the system clock has minimum loading and is used only to generate a clock signal for a small number of blocks.
To ensure correct data transfer without the use of synchronising circuits, alternate transitions (positive edges) of the system clock are ‘numbered’ All denied clocks must have their positive edges coincident with an odd numbered positive edge of the system clock, and must have their negative edges coincident with an even numbered. positive edge of the system clock Any functional block of the ASIC can (subject to the operation of a respective state machine) clock out data on the positive edge of its own clock and receive data on its negative edge Because of these rules, data cannot be clocked out of one block and into another on the same clock edge and therefore data transfer without the danger of loss can occur. without the need for ‘elastic’ buffers and/or synchronisers.
Dividing a system clock by an integer may require a clock that alternates between two frequencies, one slower and one faster than the intended frequency A special ‘logic’ clock must be generated if the logic within a block is unable to run at the higher frequency Such a special clock would not obey the rules set out above and so a retiming needs to be performed at the output of the relevant block.
There is no handshaking required between blocks in different clock domains Each block will be aware of the numbering scheme and is therefore aware when other blocks can send or receive data.
Further features of the invention will be apparent from the following detailed description with reference to the accompanying drawings.


REFERENCES:
patent: 4700350 (1987-10-01), Douglas et al.
patent: 5150364 (1992-09-01), Negus
patent: 5987083 (1999-11-01), Matsushita et al.
patent: 5999023 (1999-12-01), Kim
patent: 6040723 (2000-03-01), Sato

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