Clocking scheme and clock system for a monolithic integrated...

Details Clocking scheme and clock system for a monolithic integrated... Clocking scheme and clock system for a monolithic integrated...

2005-10-11

2005-10-11

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000

Reexamination Certificate

active

06954093

ABSTRACT:
Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1through cN) which are delayed relative to each other, wherein the individual delays (t) are distributed within a period T of the basic lock rate. Each of the N intermediate clocks (c1through cN) supplies at least one of M data-processing blocks (D1through DM). To effect a transfer of data between a transmitting data-processing block (D2) and a receiving data-processing block (D1), the delay of the intermediate clock assigned to the intermediate clock (c2) is greater than the delay of the intermediate clock (c1) assigned to the receiving data-processing block.

REFERENCES:
patent: 4618788 (1986-10-01), Backes et al.
patent: 5764083 (1998-06-01), Nguyen et al.
patent: 5929683 (1999-07-01), Menkhoff
patent: 6188262 (2001-02-01), Sutherland
patent: 0 274 606 (1987-11-01), None
patent: WO 02/01233 (2002-01-01), None

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