Clocking scheme and charge transfer switch for increasing...

Details Clocking scheme and charge transfer switch for increasing... Clocking scheme and charge transfer switch for increasing...

2000-08-31

2001-10-23

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000, C327S543000

Reexamination Certificate

active

06307425

ABSTRACT:

TECHNICAL FIELD
The present invention is directed to charge pumps used for the purpose of increasing a supply voltage to obtain a higher voltage needed to operate a circuit element, and more specifically, to a design for a charge pump having a clocking scheme and charge transfer switch which increases its efficiency. The clocking scheme and charge transfer switch may also be used to reduce the power consumption of other circuits having internal signals or nodes that are in opposite phase to each other.
BACKGROUND OF THE INVENTION
Voltage multipliers are commonly used to increase the voltage of a supply source in order to provide the higher voltages needed to operate circuit elements. One type of voltage multiplier is termed a charge pump, and is commonly used in non-volatile memory systems to provide the voltages needed for programming and erasing memory cells. A charge pump functions by progressively storing more charge on a capacitor which is part of a capacitor-diode combination, with several such stages being placed together in a network to obtain the desired increase in voltage. The diode functions to prevent discharge of the capacitor prior to its having additional charge placed on it. In charge pump designs which are fabricated using integrated circuit processing methods, both the diode and the capacitor are typically formed from properly configured transistors.
A clock signal is used to trigger the charging of the capacitor(s), with the clock frequency being such that the clock signal period is less than the discharge time of the capacitors(s. Typically, two clock signals having opposite phase are used to charge alternate stages of a multi-stage charge pump. The opposite phase clock signals are used to increase the amount of charge which can be placed on the capacitors.
FIG. 1
is a block diagram showing the components of a typical charge pump
10
. Charge pump
10
includes oscillator
12
which is used to trigger the production of the clock signals by clock generator
14
. The operation of oscillator
12
is initiated by enable signal
13
. Clock generator
14
outputs the clock signals used to control the charging of the capacitors contained in pump circuit
16
. Regulator
18
samples the output
17
of pump circuit
16
and generates reset signal
19
when pump circuit
16
outputs the appropriate voltage. Regulator
18
is used to control the operation of oscillator
12
in order to cause output
17
of pump E
4
circuit
16
to approach the desired output voltage. This is accomplished by turning oscillator
12
on or off, which in turn affects the frequency of the clock signals produced by clock generator
14
.
FIG. 2A
is a schematic diagram of a pump circuit
20
which can be used as part of a voltage multiplier, such as the charge pump of FIG.
1
. The circuit of
FIG. 2A
is representative of that found in pump circuit
16
of FIG.
1
. As shown in
FIG. 2
, the inputs to the circuit are an input supply voltage
22
and two clock signals, shown as Ph
1
23
and Ph
2
24
in the figure. As shown in
FIG. 2B
, clock signals
23
and
24
are typically square waves having opposite phases and an amplitude corresponding to the magnitude of external power supply
22
. Input supply voltage
22
provides the supply of charge for the charge pump.
Clock signals
23
and
24
are connected to alternating stages of charge pump circuit
20
, where each stage is composed of a transistor
26
configured to function as a diode, a pump capacitor
28
(labelled “C” in the figure), and a stray capacitance
30
representing the parasitic capacitance between node
27
(the charged node for that pump stage) and the substrate (labelled “C
S
” in the figure). Transistor
26
is typically configured to act as a diode by connecting the gate to the drain. Clock signal
23
or
24
is connected to one side of pump capacitor
28
, with the other side of the capacitor being connected to the diode (transistor).
As shown in the figure, a total of N such stages are connected in a serial manner, eventually producing output voltage
32
. Each stage has a diode, pump capacitor, and stray capacitance, as well as an associated clock signal. Pump capacitor
28
is typically implemented in the form of a properly configured transistor. In such a case, there is an additional stray capacitance associated with the configured transistor, the associated routing, and adjacent devices. This may be termed the stray capacitance on the clock driver side of the pump capacitor. Note that as before, there is a stray capacitance on the pumped node side (the capacitance labelled C
S
in FIG.
2
A). This clock driver side stray capacitance must be charged and discharged with each cycling of the stages of the charge pump, thereby increasing the power required to operate the pump.
The efficiency of charge pump circuit
20
is determined by the ratio of the output power to input power, and is given by:
Efficiency
=
V
out
·
I
load
V
supply
·
I
supply
V
out
=V
supply
+N•[C/(C+C
S
)•V
supply
—VTN]−VTN−V
dl
,
where
V
supply
=Supply voltage to the pump circuit (Input);
N=number of charge pump stages;
VTN=voltage drop across the diode in a pump stage;
V
dl
=voltage drop due to the load current (depends upon N, clock frequency, load current, diode resistance, and pump stage capacitance);
C=pump capacitance per stage; and
C
S
=stray capacitance per stage on the pumped node side.
Inspection of the expression for the pump efficiency shows that the efficiency may be increased by increasing V
out
or by decreasing I
supply
for a given number of stages. Previous attempts to increase the efficiency have focused on increasing V
out
. This has been accomplished by use of threshold cancellation techniques (such as those which will be described with reference to
FIG. 3
) and/or by using transistors having lower threshold voltages for the pump stage diodes. However, a disadvantage to using lower threshold voltage transistors is that they require additional manufacturing steps. V
out
can also be increased by reducing C
S
, which can be accomplished by optimizing the physical implementation of the charge pump.
FIG. 3A
is a schematic diagram for a pump circuit
50
which uses the technique of Vt (threshold voltage) cancellation to increase the output voltage (and hence efficiency) of a charge pump. The threshold voltage of a transistor configured to act as a diode corresponds to the VTN voltage drop term in the expression for the pump efficiency. As shown in
FIG. 3A
, four clock signals, labelled Ph 1
52
, Ph 1a
54
, Ph 2
56
, and Ph 2a
58
in
FIG. 3B
, are now used to control the operation of the circuit. As indicated in timing diagram
FIG. 3B
, clock signals Ph 1
52
and Ph 2
56
are typically square waves having opposite phase, while clock signals Ph 1a
54
and Ph 2a
58
are square waves that have a duty cycle that is smaller than that of signals Ph 1 and Ph 2. Signals Ph 1a
54
and Ph 2a
58
are square waves with a shorter time at which they have a high value than do signals Ph 1 and Ph 2.
Each stage of pump circuit
50
of
FIG. 3A
is composed of a switching transistor
60
(labelled “A” in the figure), a capacitor
62
connected between the gate of that transistor and a clock signal, a transistor
64
(labelled “B” in the figure) configured to act as a diode when transistor
60
is switched “on”, and a pump capacitor
66
(labelled “C” in the figure). Capacitor
68
(labelled “C
S
” in the figure) represents the stray capacitance on the charged node side for the stage of the circuit. Capacitor
76
(labelled “C
C
” in the figure) represents the stray capacitance of pump capacitor
66
on the clock side of the circuit, which arises in the case where pump capacitor
66
is implemented in the form of a properly configured transistor or another fabricated capacitor.
In the operation of circuit
50
, at time t1 (see FIG.
3
B), clock signal Ph 1
52
goes high, charging capacitor
66
and causing the node l

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