Clocking circuit with increasing delay as supply voltage VDD

Details Clocking circuit with increasing delay as supply voltage VDD Clocking circuit with increasing delay as supply voltage VDD

1994-10-07

1996-07-02

Yoo, Do Hyun

Static information storage and retrieval

Powering

365149, 365194, 365233, 327277, 327284, G11C 1300

Patent

active

055329691

ABSTRACT:
A clocking circuit and clocking method provide a clocking signal that tracks supply voltage VDD such that as supply voltage VDD increases, the signal generation delay also increases. Complementary circuit embodiments and methods are described. In one clocking circuit, a capacitive load stores an amount of charge that varies with supply voltage VDD. A discharge circuit linearly discharges the capacitive load under control of a switch which is responsive to an input signal. A detection circuit is coupled to the capacitive load for detecting linear discharging of the capacitive load to a trigger level V.sub.0 and for providing the clocking signal upon detection of the trigger level. The trigger level is predefined and substantially independent of variation in supply voltage VDD. The clocking techniques presented can be advantageously employed within memory devices such as DRAMs or SRAMs.

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Watanabe et al., "A New CR-Delay Circuit Technology for High-Density and High-Speed DRAM's," IEEE Journ. of Solid-State Circuits, vol. 24, No. 4, pp. 905-910, Aug. 1989.

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