Clocking analog components operating in a digital system

Details Clocking analog components operating in a digital system Clocking analog components operating in a digital system

2011-05-10

2011-05-10

Nguyen, Linh V (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S110000, C341S118000, C341S120000, C341S155000

Reexamination Certificate

active

07940202

ABSTRACT:
In one example, a clock generation component is configured to receive a master clock and generate a plurality of clock signals that are shifted relative to one another for a chip having an analog domain and a digital domain. A first selection component is configured to select a first one of the generated clock signals and drive the digital domain according to the first clock signal. A second selection component is configured to select a second one of the generated clock signals that is shifted relative to the first clock signal currently used to drive the digital domain for driving an analog component of the analog domain.

REFERENCES:
patent: 4504862 (1985-03-01), Achtstaetter
patent: 4908582 (1990-03-01), Kawano et al.
patent: 5049766 (1991-09-01), van Driest et al.
patent: 5373293 (1994-12-01), Hirata
patent: 5706004 (1998-01-01), Yeung
patent: 5825226 (1998-10-01), Ferraiolo et al.
patent: 5875219 (1999-02-01), Kim
patent: 6054887 (2000-04-01), Horie et al.
patent: 6154164 (2000-11-01), Gross, Jr.
patent: 6154165 (2000-11-01), Gross, Jr.
patent: 6300889 (2001-10-01), Piasecki
patent: 6351168 (2002-02-01), Li et al.
patent: 6373302 (2002-04-01), Li et al.
patent: 6686957 (2004-02-01), Johnson et al.
patent: 6700943 (2004-03-01), Miller
patent: 6836152 (2004-12-01), Karasudani
patent: 6950044 (2005-09-01), Piasecki et al.
patent: 6956518 (2005-10-01), Piasecki et al.
patent: 7496781 (2009-02-01), Tamura et al.
patent: 7609756 (2009-10-01), Wood
patent: 7620131 (2009-11-01), May et al.
patent: 7660376 (2010-02-01), Wang
patent: 7688242 (2010-03-01), Shimizu et al.
patent: 2005/0151678 (2005-07-01), Bilinskis et al.
patent: 2006/0012498 (2006-01-01), Shim et al.
patent: 2006/0038596 (2006-02-01), Wang
patent: 2006/0227019 (2006-10-01), Somayajula
patent: 2008/0030387 (2008-02-01), Sheng et al.
Actel Corporation, “Designing Clean Analog PLL Power Supply in a Mixed-Signal Environment”, May 2004, 7 pgs.
USPTO Notice of Allowance for U.S. Appl. No. 09/533,198 dated Aug. 14, 2001; 2 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 09/533,198 dated Apr. 12, 2001; 7 pages.
USPTO Notice of Allowance for U.S. Appl. No. 09/533,740 dated Sep. 10, 2001; 1 page.
USPTO Non-Final Rejection for U.S. Appl. No. 09/533,740 dated May 9, 2001; 6 pages.
RoboClockII CY7B994V/CY7B993V, “High-Speed Multi-Phase PLL Clock Buffer,” Cypress Semiconductor Corporation, Jun. 2000, pp. 1-14; 14 pages.

Affiliated with

Also associated with

Rating

Clocking analog components operating in a digital system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clocking analog components operating in a digital system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clocking analog components operating in a digital system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2698295