Clocked tri-state driver circuit

Details Clocked tri-state driver circuit Clocked tri-state driver circuit

1982-06-14

1985-03-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307270, 307453, 307481, H03K 19096, H03K 17693

Patent

active

045047456

ABSTRACT:
A tri-state driver circuit is provided having a first clock node; and a second clock node, the first and second clock nodes being adapted to receive first and second clock signals from respectively first and second clock signal sources, the first clock signal being periodic and having a first and second logic level, the second clock signal being the complement of the first clock signal. A float node is included and is adapted to receive a complement float signal (F) having a first and second logic level from a float signal source, an array of input nodes are also included, each input node being adapted to receive an input signal having a first and second logic level from a respective input signal source. An array of output nodes are included, each output node corresponding to a respective input node and being coupled to a respective load. The clocked tri-state driver circuit comprises: an enable node, a clocked power switch means coupled to the first and second clock signal nodes and the float node; the clocked power switch means being responsive to the first and second clock signal and the complement float signal first logic level for providing a clocked enable signal to the enable node; an array of driver circuit means for conditioning and transferring each respective input signal from a corresponding input node as an output signal to a corresponding output node when enabled, each respective driver circuit means being coupled to the enable node and enabled by the clocked enable signal, each respective driver circuit means being decoupled from the corresponding output node when not enabled, whereby the tri-state driver circuit operates to provide an array of output signals to an array of corresponding output nodes when enabled by the clocked enable signal first logic level at the enable node; the tri-state driver circuit also operating to decouple the output signals from the corresponding output nodes in response to the clocked enable signal second logic level thereby permitting the corresponding output nodes to be conditioned by voltage sources other than the tri-state driver circuit.

REFERENCES:
patent: 4322640 (1982-03-01), Fukushima et al.
patent: 4363978 (1982-12-01), Heimbigner
patent: 4379241 (1983-04-01), Pumo
patent: 4380709 (1983-04-01), Au
Homan, "FET Depletion Load Push-Pull Logical Circuit", IBM Tech. Disc. Bull., vol. 18, No. 3, Aug. 1975, pp. 910-911.

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