Clocked self booting logical "EXCLUSIVE OR" circuit

Details Clocked self booting logical "EXCLUSIVE OR" circuit Clocked self booting logical "EXCLUSIVE OR" circuit

1983-01-06

1985-12-31

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307453, 307481, 307482, H03K 1921, H03K 19096

Patent

active

045623651

ABSTRACT:
A solid state logical "EXCLUSIVE OR" circuit for implementation in NMOS circuitry utilizes existing non-overlapping clock pulses for self-booting circuit conditioning, enabling ultrafast propagation times and minimal power drain during circuit operation, whereof row driver circuit design concepts are utilized and silicon area is minimized and two, non-overlapping, low impedance pulses, normally present in the circuit environment are utilized.

REFERENCES:
patent: 3569729 (1971-03-01), Washizuka et al.
patent: 3579275 (1971-05-01), Polkinghorn et al.
patent: 3602732 (1971-08-01), Suzuki
patent: 3651334 (1972-03-01), Thompson et al.
patent: 4207476 (1980-06-01), Upadhyayula
patent: 4367420 (1983-01-01), Foss et al.

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