Clocked logic low power standby mode

Details Clocked logic low power standby mode Clocked logic low power standby mode

1979-12-26

1982-02-23

Smith, Jerry

Boots, shoes, and leggings

364900, G06F 104

Patent

active

043171800

ABSTRACT:
An electronic data processing system such as utilized in battery powered hand held calculators having a two mode clock control for control of power consumption. A power consumption controller enables generation of clock signals in an active cycling state for operating the data processing system in an active mode and enables generation of clock signals in a predefined steady state for operating the data processing system in a low power standby mode. In another embodiment of this invention, the power consumption controller generates a preset signal during the standby mode, this preset signal being applied to certain critical circuits of the data processing system to force each critical circuit output to a designer predefined output logic level during the standby mode. The designer predefined output logic level of each critical circuit is selected to prevent static power loads in the standby mode caused by node self discharge.

REFERENCES:
patent: 3922526 (1975-11-01), Cochran
patent: 3941989 (1976-03-01), McLaughlin et al.
patent: 3955355 (1976-05-01), Luce

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