Clocked logic delay device which corrects for the phase differen

Details Clocked logic delay device which corrects for the phase differen Clocked logic delay device which corrects for the phase differen

1984-12-24

1988-01-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307262, 328 63, 328 72, 328133, 328155, H03K 117, H03K 1700

Patent

active

047193654

ABSTRACT:
A clocked logic circuit operates in synchronism with a clock and is supplied with an input binary signal asynchronously with the clock for issuing an output binary signal. A phase detector circuit produces a phase difference signal indicating into which of k divided phase regions of one period of the clock falls, the phase difference between the input binary signal and the clock. The phase difference signal is delayed by a matching delay means for a delay approximately equal to a delay of the clocked logic circuit. An output binary signal from the clocked logic circuit is given a delay corresponding to one of the k phase regions designated by the delayed phase difference signal, and the delayed output binary signal is issued to an output terminal.

REFERENCES:
patent: 4386323 (1983-05-01), Jansen

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