Clocked latching circuit

Details Clocked latching circuit Clocked latching circuit

1983-05-13

1986-07-08

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307288, 307530, H03K 501, H03K 3286

Patent

active

045995265

ABSTRACT:
A digital latching circuit includes a quantizer having an input pair of emitter-coupled transistors connected with output transimpedance circuits. The quantizer is responsive to the state of an input signal applied to the input pair for producing from the output transimpedance circuits a quantized output signal. A feedback pair of emitter-coupled transistors is interposed between the outputs of the transimpedance circuits and the inputs to the transimpedance circuits. Current pulses are applied alternatively to the common emitter circuits of the input pair and the feedback pair of transistors for alternatively enabling the quantizing of the state of the input signal and the latching of that quantized state.

REFERENCES:
patent: 3728560 (1973-04-01), Treadway
patent: 4258273 (1981-03-01), Straznicky et al.
"A Single Chip Regenerator for Transmission Systems Operating in the Range 2-320 Mbits/S", IEEE Jour. of Solid-State Circuits, vol. SC-17, No. 3, Jun. 1982, pp. 553-558.

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