Clocked IGFET voltage level sustaining circuit

Details Clocked IGFET voltage level sustaining circuit Clocked IGFET voltage level sustaining circuit

1975-09-12

1976-10-12

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307214, 307270, 307DIG4, H03K 1908, H03K 1940

Patent

active

039860442

ABSTRACT:
A voltage level sustaining circuit for an IGFET driver circuit having an output node includes a first IGFET coupled between a voltage supply conductor and an output node of a driver circuit. The gate of the first IGFET is coupled to a source of a second IGFET having its gate and drain connected to the voltage supply conductor. A boosting capacitor is connected between the gate of the first IGFET and a conductor to which a refresh pulse is applied. The refresh pulse need be applied only often enough and be of sufficient magnitude to turn on the first IGFET sufficiently hard that the output node is held at the voltage of the voltage supply conductor.

REFERENCES:
patent: 3480796 (1969-11-01), Polkinghorn et al.
patent: 3619670 (1971-11-01), Heimbigner
patent: 3710271 (1973-01-01), Putman
patent: 3769528 (1973-10-01), Chu et al.
patent: 3778784 (1973-12-01), Karp et al.
patent: 3906464 (1975-09-01), Lattin
De Simone, "Dynamic Gating Circuit"; IBM Tech. Discl. Bull.; vol. 18, No. 3; pp. 638-639; 8/1975.

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