Clocked differential cascode voltage switch logic systems

Details Clocked differential cascode voltage switch logic systems Clocked differential cascode voltage switch logic systems

1983-11-21

1986-02-11

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307453, 307471, H03K 19017, H03K 19096, H03K 1920, H03K 1921

Patent

active

045700842

ABSTRACT:
A differential logic system is provided for a complete logic family which has a first switching circuit that produces a given output signal at a first output node and a second switching circuit that produces a second output signal which is the complement of that of the given output signal at a second output node. First and second clocked devices are connected from the first and second output nodes, respectively, to a voltage source, and first and second inverters are connected to the first and second output nodes, respectively. Additionally, a regenerative circuit may be connected between the first and second output nodes and the voltage source.

REFERENCES:
patent: 3651342 (1972-03-01), Dingwall
patent: 3911289 (1975-10-01), Takemoto
patent: 3917958 (1975-11-01), Hatsukano
patent: 4350905 (1982-09-01), Sato
patent: 4367420 (1983-01-01), Foss et al.
patent: 4401903 (1983-08-01), Iizuka
Lane, "Bipolar FET High-Speed Logic Switch"; IBM-TDB; vol. 14, No. 12, pp. 3684-3685; 5/1972.
Murphy et al, 1981 IEEE International Solid-State Circuits Conf., "A CMOS 32b Single . . ", Feb. 2, 1981, pp. 230, 231 and 276.
Krambeck et al, IEEE J. of Solid-State Circuits, "High-Speed Compact Circuits with CMOS", June 1982, vol. SC-17, No. 3, pp. 614-619.

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