Clocked comparator with offset-voltage compensation

Details Clocked comparator with offset-voltage compensation Clocked comparator with offset-voltage compensation

1992-04-13

1994-05-10

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307352, 307354, 307491, 330253, H03K 524

Patent

active

053110854

ABSTRACT:
A clocked comparator circuit comprises an input stage and a sample-and-hold circuit and an amplifier-latch circuit coupled to the output of the input stage. The sample-and-hold circuit provides an accurate offset-voltage compensation and the amplifier-latch circuit provides a high operating speed by means of a switchable current source (S6, T11). Switches are provided so that the amplifier-latch circuit constitutes a differential load having a high positive impedance during a first state of a clock signal, a low positive impedance during a next state of the clock signal, and a negative impedance during a following state of the clock signal.

REFERENCES:
patent: 4553052 (1985-11-01), Takahashi
patent: 4748346 (1988-05-01), Emori
patent: 5047666 (1991-09-01), Astegher et al.
patent: 5170079 (1992-12-01), Komatsu et al.

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