Clocked comparator with offset reduction

Details Clocked comparator with offset reduction Clocked comparator with offset reduction

1989-12-20

1991-07-02

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 307494, H03K 524

Patent

active

050288156

ABSTRACT:
In a clocked comparator with offset reduction, a differential amplifier (5) amplifies the voltage difference between the input terminals (1, 2) and the offset voltage (Voff) in a first state of a clock signal and stores said difference as a charge on the capacitors (C1, C2). In a second state of the clock signal the capacitors are coupled to the inputs (3, 4) of the differential amplifier in such a way that owing to positive feedback the differential amplifier behaves as a flip-flop whose decision threshold is independent of the offset voltage.

REFERENCES:
patent: 4553052 (1985-11-01), Takahashi
patent: 4707624 (1987-11-01), Yee

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