Clocked CMOS circuit with at least one CMOS switch

Details Clocked CMOS circuit with at least one CMOS switch Clocked CMOS circuit with at least one CMOS switch

1987-06-29

1989-01-31

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307583, 307585, 307279, 3072471, H03K 3356, H03K 3013, H03K 17687, H03K 17693

Patent

active

048018198

ABSTRACT:
To avoid interference signals caused by overlapping edges of a switching signal for driving p-channel-transistor
-channel-transistor pairs, a drive circuit contains a first series combination of the current paths of a first p-channel transistor, a first n-switching transistor, and a first n-channel transistor and a second series combination of a second p-channel transistor, a second n-switching transistor and a second n-channel transistor, with the gate of the first p-channel transistor connected to the current-path junction of the second series combination, and the gate of the second p-channel transistor connected to the current-path junction of the first series combination. The switching signal and the inverse thereof are applied to the gates of the first n-channel transistor and the second n-channel transistor, respectively. The gates of the n-switching transistors are presented with the n-clock. The first and second current-path junctions are followed by a first inverter and a second inverter, respectively. If the transistor pair is to be turned on by the L or H level of the switching signal, the gate of the n-channel transistor of the pair is connected to the first current-path junction or the second current-path junction, respectively, and the gate of the p-channel transistor to the output of the first inverter or the second inverter, respectively.

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