Clocked CMOS bus precharge circuit having level sensing

Details Clocked CMOS bus precharge circuit having level sensing Clocked CMOS bus precharge circuit having level sensing

1987-02-17

1988-08-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307362, 307451, 307481, H03K 19003, H03K 19096

Patent

active

047630230

ABSTRACT:
A circuit for charging a capacitive load such as a data or address bus in a VLSI circuit includes a voltage source input, a PFET switch connected between the voltage source input and the capacitive load or bus, and a voltage regulator connected to the capacitive load and to the gate of the PFET switch to cause the switch to conduct during a predetermined time only if the voltage on the capacitive load is less than a predetermined voltage, and to disconnect the capacitive load from the voltage source input when the voltage on the capacitive load reaches or exceeds that predetermined voltage level. The voltage regulator may include a first inverter having its input connected to the bus and a second inverter having an input connected to the output of the first inverter and having an output connected to the control input of the switch. The first inverter is constructed to output a low level when the voltage on the first inverter input is at or above the designated predetermined voltage. The predetermined voltage level is determined by the "trigger point" of the first inverter.

REFERENCES:
patent: 4498021 (1985-02-01), Uya
patent: 4598216 (1986-07-01), Lauffer et al.
patent: 4618786 (1986-10-01), Johnson
patent: 4647797 (1987-03-01), Sanwo et al.
patent: 4692639 (1987-09-01), Jordan
patent: 4700086 (1987-10-01), Ling et al.

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