Patent
1990-11-19
1992-06-02
Mintel, William
357 15, 357 42, H01L 2702
Patent
active
051191601
ABSTRACT:
Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each transistor including a source region and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a diode junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two diode junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. The transconductors of the MOS transistors is multiplied by the beta of the bipolar transistors. The ohmic contacts to the drain regions can be interconnected, and the low on resistance of the opposite polarity drive transistor extracts any excess stored charge in the drain region. Two clocked transistors interconnect the complementary insulated gate field-effect transistor pair to voltage potentials whereby operation of the integrated transistor structure is clocked.
REFERENCES:
patent: 4336550 (1982-06-01), Medwin
patent: 4694562 (1987-09-01), Iwasaki et al.
patent: 4830973 (1989-05-01), Mastroianni
patent: 4920399 (1990-04-01), Hall
patent: 4928164 (1990-05-01), Tanizawa
Loke Steven
Mintel William
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