Clocked cascading current-mode regulator with high noise...

Details Clocked cascading current-mode regulator with high noise... Clocked cascading current-mode regulator with high noise...

2006-02-21

2006-02-21

Riley, Shawn (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

Reexamination Certificate

active

07002325

ABSTRACT:
A clocked cascadable power regulator including synchronization logic and PWM control logic. The synchronization logic receives a clock signal and asserts a digital output signal synchronized with the clock signal in response to assertion of a digital input signal. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The regulator may be used alone or cascaded with other similar regulators for implementing a multiphase power converter with multiple channels. The clocked cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. In the cascaded configuration, there is one clock common to all channels which ensures that the phase separation between the channels is symmetrical to within the jitter tolerance of the common clock.

REFERENCES:
patent: 6043634 (2000-03-01), Nguyen et al.
patent: 6218815 (2001-04-01), Kates et al.
patent: 6366069 (2002-04-01), Nguyen et al.
patent: 6448746 (2002-09-01), Carlson
patent: 6628106 (2003-09-01), Batarseh et al.

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