Clocked buffer circuit using a self-bootstrapping transistor

Details Clocked buffer circuit using a self-bootstrapping transistor Clocked buffer circuit using a self-bootstrapping transistor

1983-03-07

1985-09-10

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307453, 307481, 307482, 307578, H03K 3027, H03K 458, H03K 1704, H03K 19017

Patent

active

045408980

ABSTRACT:
A clocked buffer circuit is provided which uses a self-bootstrapping transistor to provide a full power supply output signal in response to an input signal and a full power supply clock signal. The self-bootstrapping transistor is disabled by a delay circuit prior to the removal of the clock signal so that the output signal is still provided after the removal of the clock signal. That the output signal reaches full power supply is ensured because the disabling effect of the delay circuit is triggered by the output signal itself.

REFERENCES:
patent: 3774055 (1973-11-01), Bapat
patent: 3903431 (1975-02-01), Heeren
patent: 3989955 (1976-11-01), Suzuki
patent: 4090096 (1978-05-01), Nagami
patent: 4381460 (1983-04-01), Menachem

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