Clocked buffer circuit

Details Clocked buffer circuit Clocked buffer circuit

1987-06-15

1988-02-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 307453, 307449, 365230, H03K 19094

Patent

active

047272678

ABSTRACT:
The present invention is especially directed towards an improved clocked buffer circuit that will clock, decode, repeat and invert an input signal. The clocked buffer circuit uses a clocked latch coupled to a decode circuit such that not only will the applied clock signal control the decode circuit, but the output of the latch will also control the decode circuit thus assuring the output of the decode circuit becomes latched into the set by the input clock signal.

REFERENCES:
patent: 3902082 (1975-08-01), Proebsting et al.
patent: 3940747 (1976-02-01), Kuo et al.
patent: 3942160 (1976-03-01), Yu
patent: 4057787 (1977-11-01), Heuner et al.

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