Clock wave noise reducer

Details Clock wave noise reducer Clock wave noise reducer

2000-02-15

2001-10-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S108000, C330S258000

Reexamination Certificate

active

06310495

ABSTRACT:

FIELD OF THE INVENTION
The present invention further relates to integrated circuit clock circuitry, and more particularly to such clock circuitry including a differential driver for deriving a pair of complementary clock waves coupled to a differential clock wave receiver via a pair of clock lines carrying complementary clock waves from the driver to a pair of differential inputs of the receiver. Another aspect of the invention relates to a circuit for removing common mode components from a pair of complementary bi-level waveforms wherein the circuit includes a differential amplifier for subtracting the common mode components during first half cycles of the waveform and for supplying an output terminal with a power supply voltage during second half cycles of the waveforms.
BACKGROUND OF THE INVENTION
An integrated circuit (IC) chip frequently includes clock trees to distribute clock waves to physically separated destination (i.e., receiver) circuits. Typically, an off-chip, external clock source provides clock waves to a plurality of clock tree branches or segments resident on the IC chip. Each branch or segment of the clock tree carries clock waves to a respective one of the physically separated destination circuits.
FIG. 1
is a circuit diagram of a conventional clock tree distribution segment for distributing clock waves on an IC chip carrying the segment. The circuit of
FIG. 1
is on an IC chip and includes spaced clock wave driver
4
and clock wave receiver
6
as well as wire or clock line
2
that is connected between the driver and receiver. Driver
4
responds to clock waves in the form of a sequence of clock pulses derived from a clock source (not shown) that, in some instances, is not on the IC chip. Driver
4
derives at output terminal
10
a sequence of amplified clock waves in the form of clock pulses. Terminal
10
, at the junction of the drains of complementary field effect transistors
11
and
13
having gates driven in parallel by the clock pulses from clock input
12
, is connected to a first end of single ended line
2
to supply the derived clock pulses to the first end of the clock line. The clock waves traverse clock line
2
and exit at a second end thereof to be injected into input terminal
14
of clock wave receiver
6
.
Receiver
6
includes complementary FETs
17
and
19
having gates driven in parallel by the pulses at terminal
14
of line
2
and drains connected to a common terminal
16
, where the output is derived. The FETs of driver
4
and receiver
6
are connected across power supply rails connected to DC power supply terminals +Vdd and ground so the sources of N-channel FETs
11
and
17
are grounded and the sources of P-channel FETs
13
and
19
are at +Vdd; in the typical prior art circuit, Vdd=3 Volts. The clock pulses propagating along line
2
are attenuated because of the substantial impedance of the line, are phased delayed because of the substantial resistance-capacitance (RC) time constant of the line, and are subject to noise on the line which is coupled to terminal
14
. Receiver
6
responds to the degraded clock pulses at terminal
14
to amplify the pulses almost to the rail-to-rail voltages +Vdd and ground.
Clock circuitry on the IC chip is subject to noise and problems associated therewith. Particularly, noise is introduced onto the single ended clock line coupled between the single ended driver and single ended receiver pair associated with that clock line. The amount of noise coupled to clock lines increases with increases in IC chip size, since the clock lines are necessarily longer in the larger chips.
In the conventional, prior art clock circuit of
FIG. 1
, noise introduced onto clock line
2
corrupts the integrity of the clock pulses propagating between driver
4
and receiver
6
. Since receiver
6
is not inherently immune to noise and does not provide noise correction or elimination, clock line noise arriving at input terminal
14
of receiver
6
is simply coupled to the output of receiver
6
, and/or the noise translates to clock jitter at the receiver output terminal
16
. Clock pulses with substantial noise components superimposed thereon arrive at destination circuits responsive to the output of receiver
6
. Under such conditions, the destination circuits of the IC chip usually do not have optimum performance. Thus, there is a need to eliminate or substantially reduce the effects of noise introduced onto the clock lines between the driver and receiver of a clock circuit, to provide a substantially noise free clock wave to a destination circuit on the IC chip.
In summary, there is a need to provide IC chip clock circuitry that both reduces clock skew and/or minimizes the deleterious effects caused by noise coupled onto clock lines in the chip. There is a further need to achieve these goals in the environment of large IC chips operating at high frequencies.
SUMMARY OF THE INVENTION
An object of the present invention is to provide new and improved clock circuitry arranged to minimize the deleterious effects caused by noise coupled onto clock lines in an IC chip.
Another object of the invention is to provide a new and improved circuit for removing common mode components from a pair of complementary bi-level waveforms.
In one aspect of the present invention, a clock circuit on an IC chip includes a driver having first and second outputs for respectively deriving first and second complementary clock waves responsive to a clock wave of a clock wave source. A receiver of the clock circuit includes first and second inputs. The clock circuit includes first and second clock lines connected respectively between the first and second outputs of the driver and the first and second inputs of the receiver. The first and second clock lines are arranged on the IC chip so that noise coupled to one of the first and second clock lines tends to be coupled to the other clock line. The receiver is constructed and arranged to substantially reject noise of like amplitude and polarity coupled to the first and second inputs of the receiver by the first and second clock lines.
In another aspect of the present invention, a clock circuit on an IC chip includes a driver having first and second outputs for respectively deriving first and second complementary clock waves responsive to a clock wave of a clock wave source. A receiver of the clock circuit includes first and second inputs. First and second clock lines are respectively connected between the first and second outputs of the driver and the first and second inputs of the receiver. The receiver is constructed and arranged to amplify clock waves having relatively low amplitudes at the first and second inputs substantially to high and low power supply voltages of the IC chip. An amplified clock wave is derived at an output of the receiver. The amplified clock wave has clock wave transitions substantially coincident with clock wave transitions of the clock wave of the clock wave source.
Another aspect of the invention relates to a circuit for removing common mode components from first and second complementary bi-level waveforms. The circuit includes first and second input terminals respectively responsive to the first and second waveforms and a differential amplifier connected to the first and second input terminals and to first and second DC power supply terminals. The differential amplifier is arranged so that during first half cycles of the waveforms, the common mode components are subtracted therein and during second half cycles of the waveforms an output terminal of the amplifier is supplied with one of the DC power supply voltages. Preferably two such similar differential amplifiers are provided. The first differential amplifier is arranged so that during the first half cycles the common mode components are subtracted therein. During the second half cycles the first amplifier supplies a first output terminal with a first DC power supply voltage. The second differential amplifier is arranged so that during the second half cycles the common mode compon

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