Clock voltage generator for semiconductor memory with reduced po

Details Clock voltage generator for semiconductor memory with reduced po Clock voltage generator for semiconductor memory with reduced po

1978-09-07

1980-12-16

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307251, 307DIG4, H03K 5135, H03K 1716, H03K 17284

Patent

active

042399904

ABSTRACT:
A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides precise control of the delay over a wide range. Power dissipation is reduced in the driver circuit by avoiding the possibility of d.c. current paths when the reset clock goes high.

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Kruggel et al, "Field-Effect Transistor Driver Circuit", IBM Tech. Discl. Bull.; vol. 18, No. 4, p. 1030; 9/1975.
Anderson et al., "FET Inverter and Driver Circuit", IBM Tech. Discl. Bull., vol. 16, No. 1, pp. 50-51; 6/1973.
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Danielski et al., "Single Input Driver Circuit", IBM Tech. Discl. Bull.; vol. 1033-4; 9/1975.

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