Clock tree adjustable buffer

Details Clock tree adjustable buffer Clock tree adjustable buffer

2011-03-29

2011-03-29

Levin, Naum B (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S105000, C326S038000, C326S095000, C327S149000, C327S161000, C327S276000

Reexamination Certificate

active

07917875

ABSTRACT:
An adjustable buffer including a series of P-channel devices having current paths coupled between a first voltage supply and at least one output node, and a series of N-channel devices having current paths coupled between the output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the output node. The selectable connections may be defined in an integrated circuit mask or may be electronic switches. The P- and N-channel devices may be in a balanced configuration or an imbalanced configuration. The P- and N-channel devices may form an inverting buffer or a non-inverting buffer.

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