Clock timing recovery using arbitrary sampling frequency

Details Clock timing recovery using arbitrary sampling frequency Clock timing recovery using arbitrary sampling frequency

2006-07-04

2006-07-04

Ghayour, Mohammed (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S374000, C327S141000

Reexamination Certificate

active

07072431

ABSTRACT:
A bit timing signal is regenerated from an encoded digital signal in a receiver using a predetermined sample rate Fs. An input pulse signal is generated in response to predetermined transitions of the encoded digital signal. A clock count signal is generated having a variable clock period according to cyclical counting of the clock count signal up to a count value S at the predetermined sample rate, the count value alternating between an upper value Suand a lower value Slso that the variable clock period has an average length substantially equal to a data bit period of the encoded digital signal. The clock count signal is synchronized with the encoded digital signal by 1) counting the input pulse signals to generate a pulse count, 2) counting sampling periods between successive input pulse signals to generate a sample count, and 3) generating a sync signal if the pulse count is greater than a pulse threshold and the sample count is greater than a sample threshold. The clock count signal and the pulse count are reset in response to the sync signal.

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