Clock timing controller for a plurality of LSI chips

Details Clock timing controller for a plurality of LSI chips Clock timing controller for a plurality of LSI chips

1988-03-25

1989-06-27

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307518, 328 75, G06F 104, H03K 515

Patent

active

048432636

ABSTRACT:
LSI chips are divided into a first chip and a plurality of second chips, and each of the first and second chips has a frequency divider for deriving a lower-frequency output clock signal from a higher-frequency input clock signal. A higher-frequency input clock signal is supplied to the first chip from an external clock source to produce a lower-frequency output clock signal. One of the second chips is selected by a chip selector and its clock output is applied to a phase comparator for comparison with the clock output of the first chip for generating a phase difference signal in response to a phase difference between the compared output clock signals. Gate circuits are enabled in the absence of the phase difference signal to supply the input clock signal to all of the second chips. The chip selector is shifted to the next one of the second chips in response to a chip selection signal in the absence of the phase difference signal. In the presence of a phase difference signal, one of the gate circuits which is associated with the selected chip is disabled to inhibit the application of the clock signal to the LSI chip in which synchronization slippage has occurred.

REFERENCES:
patent: 4137563 (1979-01-01), Tsunuda
patent: 4613775 (1986-09-01), Dick
patent: 4691124 (1987-09-01), Ledzius et al.

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