Clock synthesizer with programmable input-output phase...

Details Clock synthesizer with programmable input-output phase... Clock synthesizer with programmable input-output phase...

1999-08-04

2002-03-12

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

C327S276000, C327S299000

Reexamination Certificate

active

06356122

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a clock synthesizer with a programmable input-output phase relationship generally and, more particularly, to a PLL-based clock synthesizer with a programmable input-output phase relationship for generating output frequencies based on a reference clock input.
BACKGROUND OF THE INVENTION
A PLL-based clock synthesizer generates output frequencies based on a reference clock input. The output clock frequency usually has no integral relationship (i.e., the ratio of the output clock frequency to an input clock frequency (or vice-versa) is an integer) to the input clock frequency. However, the input and output clocks are related by the relationship that there are Q cycles of the input clock for every P cycles of the output clock, where P and Q are integers. In some cases, it may be useful to have a known phase relationship between the input and output clocks. This is most often the case when either P/Q or Q/P is an integer, but that is not always required. The input-output delay depends on the difference between the delay of the logic in the reference path and the delay in the logic of the output path (which begins at the phase detector inputs, where the phase error is zero). The logic delays are delays through multiplexers, counters, post-dividers, etc.
The phase relationship in a zero-delay buffer may depend on the location of a tap in the feedback path in the ring oscillator. Additionally, zero-delay buffers usually have dividers either in the reference path or the feedback path. Thus, zero-delay buffers tend to be less flexible than a PLL as a clock generator.
FIG. 1
illustrates a block diagram of a conventional zero-delay buffer architecture.
Conventional method(s) have the disadvantages of unpredictable input-output phase relationship and/or less flexibility. However, many applications for clock synthesizers benefit from a predictable input-output phase relationship, when the output frequency is a multiple of the input frequency. The present invention enjoys particular advantages in applications where a predictable input-output phase relationship is desired, particularly where the output frequency is an integral or one-half an integral multiple of the input frequency.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising an oscillator, a reference path, and a feedback path. The oscillator may have a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output. The reference path may provide the reference signal from a reference clock input. The feedback path may provide the feedback signal from the oscillator loop output. At least one of the reference path and the feedback path comprises a programmable delay circuit.
The objects, features and advantages of the present invention include providing a clock synthesizer that may (i) implement a programmable input-output phase relationship, (ii) provide user programmable inputs for a programmable phase relationship and/or (iii) implement a programmable phase relationship in reference and/or feedback paths that may implement an oscillator in a phase locked loop.


REFERENCES:
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patent: 5446867 (1995-08-01), Young et al.
patent: 5687202 (1997-11-01), Eitrheim
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5933032 (1999-08-01), Shah et al.
patent: 5936451 (1999-08-01), Phillips et al.
patent: 5936977 (1999-08-01), Churchill et al.
patent: 6043717 (2000-03-01), Kurd
Cypress RoboClockII™ CY7B994V/CY7B993V, “High-Speed Multi-Phase PLL Clock Buffer”, December 1998, p. 1.
Cypress CY2308, “3.3V Zero Delay Buffer”, Jun. 27, 1997, pp. 1-7.

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