Clock synthesizer with clock divider outside feedback loop...

Details Clock synthesizer with clock divider outside feedback loop... Clock synthesizer with clock divider outside feedback loop...

2006-10-04

2008-12-09

Kinkead, Arnold (Department: 2817)

Oscillators

Combined with particular output coupling network

C331S025000, C327S156000, C375S376000

Reexamination Certificate

active

07463102

ABSTRACT:
A de-skew multiplier clock synthesizer with a clock divider outside the feedback loop of a PLL is provided. The clock synthesizer includes a phase locked loop (PLL), a clock divider, and a phase comparator. The PLL receives a reference clock and generates a PLL output clock. The clock divider receives the PLL output clock and generates a first output clock. The phase comparator receives the reference clock, the PLL output clock, and the first output clock and generates a phase difference signal. The clock divider adjusts the first output clock to be in phase with the reference clock according to the phase difference signal.

REFERENCES:
patent: 5811998 (1998-09-01), Lundberg et al.

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