Clock synchronous type semiconductor memory device that can swit

Static information storage and retrieval – Addressing – Sync/clocking

Patent

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Details

36523003, 365 51, 365 63, 365190, 365191, 365220, 365221, 36518905, 36518901, 365194, 365195, 365168, 365205, G11C 800

Patent

active

06166989&

ABSTRACT:
Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

REFERENCES:
patent: 5903514 (1999-05-01), Sawada

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