Clock synchronous type semiconductor memory device that can...

Details Clock synchronous type semiconductor memory device that can... Clock synchronous type semiconductor memory device that can...

2000-09-20

2002-04-23

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S201000, C365S202000, C365S207000, C365S208000, C365S190000, C365S051000, C365S063000

Reexamination Certificate

active

06377512

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, particularly to a clock synchronous semiconductor memory device that operates in synchronization with a clock signal. More particularly, the present invention relates to the structure of an internal data transfer scheme of a clock synchronous semiconductor memory device that can switch the word configuration.
2. Description of the Background Art
FIG. 58
schematically shows an entire structure of a conventional synchronous semiconductor memory device. Referring to
FIG. 58
, a synchronous semiconductor memory device
900
includes memory arrays MAa, MAb, MAc and MAd each having a plurality of memory cells arranged in rows and columns, multibit internal data buses
910
a
-
910
d
provided corresponding to memory arrays MAa, MAb, MAc and MAd, respectively, a selector/driver
915
selecting bus lines of multibit internal data buses
910
a
-
910
d
according to an address signal CA and a select signal &phgr;sel, an internal read data bus
920
transmitting data from selector/driver
915
, and an output circuit OB generating external data according to data applied through internal read data bus
920
.
Memory arrays MAa-MAd form banks #
0
-#
3
, respectively, and are driven to a selected state independent of each other. Here, “a selected state” refers to the state where a word line is driven to a selected state in a memory array and the data in a memory cell connected to the selected word line is retained.
Select signal &phgr;sel is set selectively and fixedly according to the bit width of output data DQ from output circuit OB. One chip can accommodate a plurality of word configurations such as ×4, ×8, ×16 and ×32 bits.
The reason why multibit internal data buses
910
a
-
910
d
are provided corresponding to memory arrays MAa-MAd, respectively, is described in the following. Banks #
0
-#
3
are driven to a selected state independent of each other, so that a plurality of banks can be maintained at a selected state. However, the access operation of writing/reading data with respect to a memory cell is carried out for one bank. The number of these banks can be altered. Therefore, internal data buses
910
a
-
910
d
are provided corresponding to memory arrays MAa-MAd, respectively, in order to readily accommodate an arbitrary bank configuration. The bit width of internal data buses
910
a
-
910
d
is equal to the bit width of internal read bus
920
. Selector/driver
915
selects an internal data bus according to a selected bank to be coupled to internal read data bus
920
. Selector/driver
915
is responsive to select signal &phgr;sel and address signal CA for switching the bus connection path according to a bit width of output data DQ.
FIG. 59
schematically shows a structure of selector/driver
915
. The circuitry for one internal data bus is shown as a representative in FIG.
59
. Internal data bus
910
(
910
a
~
910
d
) includes bus lines
910
-
0
~
910
-
3
of 4 bits. The output data of preamplifiers
925
-
0
~
925
-
3
that amplify memory cell data IO
0
-IO
3
are transmitted to data bus lines
910
-
0
~
910
-
3
, respectively.
Similarly, read data bus
920
includes read data bus lines
920
-
0
~
920
-
3
of 4 bits. Output circuits OB
0
-OB
3
are provided for these read data bus lines
920
-
0
~
920
-
3
, respectively. Output data DQ
0
-DQ
3
are provided from output circuits OB
0
-OB
3
, respectively.
Selector/driver
915
includes an OR circuit
915
a
receiving address signal CA and select signal &phgr;sel, an inverter
915
b
inverting the output signal of OR circuit
915
a
, drive circuits DV
0
-DV
3
provided corresponding to read data bus lines
920
-
0
~
920
-
3
, respectively, a transfer gate TX
0
coupling data bus line
910
-
0
to the input of drive circuit DV
1
according to the output signal of inverter
915
b
, a transfer gate TX
1
coupling data bus line
910
-
1
to the input of drive circuit DV
1
according to the output signal of OR circuit
915
a
, a transfer gate TX
2
coupling data bus line
910
-
2
to the input unit of data circuit DV
3
according to the output signal of inverter
915
b
, and a transfer gate TX
3
coupling data bus line
910
-
3
to the input of drive circuit DV
3
according to the output signal of OR circuit
915
a
. Drive circuits DV
0
and DV
2
are enabled when select signal &phgr;sel is at an H level (logical high), to drive read data bus lines
920
-
0
~
920
-
2
according to the data read out on data bus lines
910
-
0
and
910
-
2
.
Select signal &phgr;sel indicates a ×4-bit configuration and a ×2-bit configuration for the word configuration (number of output data bits) at an H level and an L level (logical low), respectively. The operation of selector/driver
915
of
FIG. 59
will be described briefly now.
When the word configuration corresponds to a ×4-bit configuration, select signal &phgr;sel is fixed at an H level. In this state, the output signal of OR circuit
915
a
is at an H level. Transfer gates TX
1
and TX
3
are conductive, and transfer gates TX
0
and TX
2
are non-conductive. Also, drive circuits DV
0
and DV
2
are set at an operable state. Therefore, read data bus lines
920
-
0
~
920
-
3
are driven by drive circuits DV
0
-DV
3
according to the data transmitted through data bus lines
910
-
0
~
910
-
3
, whereby 4 bits of data DQ
0
-DQ
3
are output via output circuits OB
0
-OB
3
.
When select signal &phgr;sel is at an L level, drive circuits DV
0
and DV
2
are set at operation disabled state. Under this state, transfer gates TX
0
-TX
3
are selectively rendered conductive according to the H level/L level of address signal CA. When address signal CA is at an H level, OR circuit
915
a
provides an output signal of an H level. Transfer gates TX
1
and TX
3
are rendered conductive. Data bus lines
910
-
1
and
910
-
3
are coupled to drive circuits DV
1
and DV
3
, respectively. Therefore, memory cell data IO
1
and IO
3
are transmitted to output circuits OB
1
and OB
3
, respectively, whereby data DQ
1
and DQ
3
are generated. When address signal CA is at an H level, transfer gates TX
1
and TX
3
are rendered non-conductive, whereas transfer gates TX
0
and TX
2
are rendered conductive. Data bus lines
910
-
0
and
910
-
2
are coupled to drive circuits DV
1
and DV
3
, respectively. In this case, memory cell data IO
0
and IO
2
are transmitted to output circuits OB
1
and OB
3
, whereby data bits DQ
1
and Q
3
are generated. As a result, data of a 2-bit configuration is output. Output circuits OB
0
and OB
2
are set at a non-operable state when the word configuration corresponds to a ×2-bit configuration.
By employing selector/driver
915
shown in
FIG. 59
, a plurality of word configurations can be accommodated without modifying the internal circuit configuration.
When data buses are arranged corresponding to respective memory arrays MAa-MAd as shown in
FIG. 58
, the area occupied by the data buses increases. Particularly in the case where the word configuration is as large as ×16 bits or ×32 bits, the area occupied by the buses becomes large. In a case of switching the bus connection according to the word configuration by use of selector/driver
915
, signal propagation is delayed in the transfer gate that switches the connection, leading to a problem that a signal cannot be transmitted at high speed. Particularly in the case where the word configuration is switched between ×16 bits and ×32 bits, the number of the transfer gates for this selector/driver is increased to result in a larger occupying area. When the number of word configurations that can be selected is increased so that any of ×4, ×8 and ×16, can be selected, the selector/driver requires the select operation of three stages, i.e. the selection of 16 bits from 32 bits, the selection of 8 bits from 16 bits, and the selection of 4 bits from 8 bits. The occupying area of this selector/driver is increased, which f

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