Clock-synchronous type semiconductor memory device capable of ou

Details Clock-synchronous type semiconductor memory device capable of ou Clock-synchronous type semiconductor memory device capable of ou

1998-07-09

1999-10-05

Le, Vu A.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 327141, 327147, 327153, G11C 700

Patent

active

059635029

ABSTRACT:
A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

REFERENCES:
patent: 5708611 (1998-01-01), Iwamoto et al.
patent: 5754490 (1998-05-01), Harrison et al.
patent: 5831929 (1998-11-01), Manning
"400 Mb/s/pin SLDRAM", 1997, SLDRAM Consortium, pp. 1-59.

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