Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-01-03
2004-06-29
Le, Thong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S220000, C365S221000
Reexamination Certificate
active
06757212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to a construction of a data output section of a clock synchronous type semiconductor memory that is operated synchronized with a clock signal externally applied. More specifically, the present invention relates to a construction that is capable of transmitting internal data at high speed in a clock synchronous type semiconductor memory.
2. Description of the Background Art
FIG. 37
is a diagram schematically showing a portion related to a data reading in a conventional clock synchronous type semiconductor memory device. In
FIG. 37
, the data reading section includes: an internal clock generation circuit
1
for buffering an external clock signal CLKe to generate an internal clock signal CLKi, a clock control circuit
2
for generating various control clock signals such as CLKR and CLKO in accordance with internal clock signal CLKi and an operation mode instruction (command) from an address/command control circuit
3
, address/command control circuit
3
for receiving an address and a command ACG and for generating an internal address and an operation mode instruction signal, a memory circuit
4
for reading stored data from a memory cell under a control of address/command control circuit
3
, a reading circuit
5
for transferring data read from a selected memory cell of memory circuit
4
in accordance with read out clock signal CLKR from clock control circuit
2
, and an output control circuit
6
for transferring data transferred from reading circuit
5
in accordance with output clock signal CLKO from clock control circuit
2
to generate an external read data Q.
In accordance with the address and command ACG, address/command control circuit
3
applies a command for specifying a data reading instruction to clock control circuit
2
in reading data. Address/command control circuit
3
also applies a reading instruction signal for instructing a data reading operation to memory circuit
4
together with an address signal.
Memory circuit
4
includes memory cells that are arranged in rows and columns, and a memory cell selection circuit for selecting a row and column of the memory cells in accordance with the internal address signal from address/command control circuit
3
. Reading circuit
5
, the construction of which will be described later, includes a preamplifier and a shifter, amplifies data of the selected memory cell of memory circuit
4
, and transfers the resultant signal in accordance with reading clock signal CLKR.
Output control circuit
6
, the construction of which will be described later, takes in data transferred from reading circuit
5
in accordance with output clock signal CLKO, executes a buffering process on the data for external output. Both of these reading clock signal CLKR and output clock signal CLKO are generated by using a delay circuit, etc., based upon internal clock signal CLKi.
In the synchronous type semiconductor memory device shown in
FIG. 37
, an address/command capturing is carried out in synchronization with a rising or falling edge of internal clock signal CLKi generated by buffering external clock signal CLKe, and internal read out data is transferred in accordance with reading clock signal CLKR. Then, output control circuit
6
buffers the internal read out data in synchronization with a rising or falling edge of output clock signal CLKO to generate external data Q. When this semiconductor memory device is operated in a signal data rate mode, the external data outputting is carried out in response to one of rising and falling edges of internal clock CLKi. In contrast, when this semiconductor memory device is operated in a double data rate mode, the data outputting is carried out in response to both of the rising and falling edges of internal clock CLKi.
FIG. 38
is a diagram schematically showing the construction of reading circuit
5
shown in FIG.
37
. In reading circuit
5
, data of a plurality of bits that is read out in parallel with each other from memory circuit
4
is selectively transferred to an internal read data line
10
.
FIG. 38
schematically shows the construction related to one-bit data.
In
FIG. 38
, reading circuit
5
includes a preamplifier
5
a
that amplifies data read out on a pair of internal data lines IO and ZIO from memory circuit
4
in response to the activation of a preamplifier activation signal PAEj, and a shifter
5
b
that transfers the amplified data of preamplifier
5
a
in synchronization with shift clock signal CLKf. This shifter
5
b
includes an output driver for driving an internal read data transmission line
10
. Preamplifiers
5
a
are placed in parallel with each other for internal read data transmission line
10
so that an output signal of the preamplifier activated by preamplifier activation signal PAEj is transmitted to internal read data transmission line
10
through the corresponding shifter.
Preamplifier activation signal PAEj is generated based upon a main preamplifier activation signal PAE and a preamplifier selection signal, and used for activating one of a plurality of preamplifiers placed in parallel with each other. Shifter
5
b
, which is a column latency shifter, carries out a transferring operation in a (column latency—2) cycle period, and adjusts the transfer period of the internal data so that, after a lapse of the column latency period since the receipt of a read command, valid data is externally outputted. A shift clock signal CLKf is generated based upon internal clock signal CLKi and the preamplifier selection signal so that the shift clock signal is applied to the shifter that is arranged in associated with the selected preamplifier.
A read data driver may be placed at an output section of this shifter
5
b
. Through internal read data transmission line
10
, upon reading data, data Qi of one bit is transferred in accordance with internal clock signal CLKi. Preamplifier activation signal PAEj and a selection signal SELj are respectively generated based upon the column address signal, and the activation timings thereof are determined based upon internal clock signal CLKi.
FIG. 39
is a diagram schematically showing the construction of output control circuit
6
shown in FIG.
37
. In
FIG. 39
, output control circuit
6
includes a read data detector
6
a
for taking in and amplifying internal reading data Qi on internal read data transmission line
10
in response to the activation of a detector enable signal DEN, and an output buffer circuit
6
b
for transferring the amplified data received from read data detector
6
a
to generate external output data Q, in accordance with an output clock signal CLKQ.
Read data detector
6
a
latches read out data Qi in synchronization with internal clock signal CLKi, and amplifies the latched data to apply the resultant data to output buffer circuit
6
b
. Output clock signal CLKO, shown in
FIG. 37
, corresponds to a pair of read data detector enable signal DEN and output signal CLKQ, and output clock signal CLKQ is generated by delaying internal clock signal CLKi by a predetermined period of time in reading data. In the same manner, detector enable signal DEN is also activated after a lapse of a predetermined time period based upon internal clock signal CLKi.
The delay times of these signals DEN and CLKQ are adjusted in accordance with the frequency of clock signal CLKi, and also changed in accordance with the frequency of clock signal CLKi.
Therefore, in this output control circuit
6
also, the data amplifying and transferring operations are carried out in synchronization with internal clock signal CLKi so that output data Q is outputted in synchronization with internal clock signal CLKi.
FIG. 40
is a timing chart representing the data reading operation of reading circuit
5
shown in FIG.
38
. As shown in
FIG. 40
, upon receipt of the read command instructing a data reading operation, a read activation signal RP is activated for a predetermined period (during a burst length pe
Hamamoto Takeshi
Miki Takeo
Le Thong
McDermott & Will & Emery
Renesas Technology Corp.
LandOfFree
Clock synchronous type semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock synchronous type semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock synchronous type semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3365427