Clock-synchronous system

Details Clock-synchronous system Clock-synchronous system

1999-11-23

2001-02-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S191000, C365S194000

Reexamination Certificate

active

06185150

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock-synchronous system which is controlled in synchronization with a clock signal and which is applied to a semiconductor memory device, such as a synchronous dynamic random access memory (DRAM), and more particularly to a command receiver which receives a plurality of commands to instruct the system to perform various modes of operation.
This application is related to U.S. patent applications Ser. Nos. 09/305,752, 09/354,102, 09/383,193 and based on Japanese Patent Application No. 10-337114 filed Nov. 27, 1998, the contents of which are incorporated herein by reference and constitute part of the specification. The present invention is effectively used with high-speed semiconductor devices disclosed in U.S. patent applications Ser. Nos. 09/305,752, 09/354,102, and 09/383,193.
For example, in a system which is controlled in synchronization with a clock signal, as in a synchronous DRAM, an operating command is required to specify a certain operation mode. This command is formed from a plurality of signals. A plurality of commands is represented by combinations of the levels of those signals.
FIG. 4
shows an example of a conventional command receiver, which is composed of receiver circuits
11
-
0
,
11
-
1
,
11
-
2
,
11
-
3
, etc. The receiver circuits are respectively supplied with signals /CMD
0
, /CMD
1
, /CMD
2
, /CMD
3
, etc. that represent a command. Here, / indicates that the corresponding signal is active when it is at a low level. For example, the signals /CMD
0
, /CMD
1
, /CMD
2
, /CMD
3
are a row address strobe signal /RAS, a column address signal /CAS, a write enable signal /WE, and an address signal /AD, respectively. The receiver circuits
11
-
0
,
11
-
1
,
11
-
2
,
11
-
3
, etc. are simultaneously activated by a command latch signal CL. The receiver circuits
11
-
0
,
11
-
1
,
11
-
2
,
11
-
3
, etc. latch the signals /CMD
0
, /CMD
1
, /CMD
2
, /CMD
3
, etc. with each cycle of the command latch signal CL and then output internal signals ICMD
0
, ICMD
1
, ICMD
2
, ICMD
3
, etc., which in turn are decoded by a decoder circuit not shown to produce a command.
FIG. 5
is a timing diagram illustrating the conventional command latch operation. The receiver circuits receive the signals /CMDi (i=0, 1, 2, . . . ) with each clock cycle of the command latch signal CL. When a combination of levels of those signals /CMDi corresponds to a given command, the system is placed in the operation mode that corresponds to that command. However, it is not known when each of the signals /CMDi changes and it is therefore required to generate the command latch signal CL for driving the receiver circuits with each cycle of the clock signal CLK.
FIG. 6
shows an example of the receiver circuit (CRCV) shown in FIG.
4
. The receiver circuit (CRCV) is composed of a receiver circuit (RCV) and a flip-flop circuit FF connected to the outputs of the receiver circuit RCV. The receiver circuit RCV provides an output signal in the form of a pulse as will be described later. To produce a stable command from the pulse-form output signal, the outputs of the receiver circuit RCV are connected to the flip-flop circuit FF consisting of two cross-coupled NOR circuits.
FIG. 7
shows the operation of the circuit shown in FIG.
6
. As shown, the flip-flop circuit FF holds the pulse-form signal /D or D output from the receiver circuit RCV and produces an internal signal ICMD. In this example, the flip-flop circuit FF receives the output signal /D to produce the internal signal ICMD and holds the state of the internal signal ICMD until the output signal D is received. By producing a command by combining internal signals ICMD having their respective state held in this manner, the state of the command is held stably. For this reason, the operation mode of the system that corresponds to the command can be held stably without using any special circuit.
FIG. 8
shows an example of the receiver circuit RCV shown in FIG.
6
. This receiver circuit is formed of P-channel MOS transistors P
1
to P
5
, N-channel MOS transistors N
1
to N
7
, and inverters I
1
and I
2
. The transistor N
4
is supplied at its gate with a signal /CMD forming a command and the transistor N
6
is supplied at its gate with a reference voltage Vref. The command latch signal CL is applied to the gates of the transistors N
3
, P
3
, P
4
and P
5
.
FIG. 9
is a timing diagram illustrating the operation of the circuit of FIG.
8
. The operation of the receiver circuit RCV shown in
FIG. 8
will now be described with reference to this timing diagram. When the command latch signal CL goes to a high level as shown in
FIG. 9
, the transistor N
3
is activated and the transistors P
3
to P
5
are deactivated. The transistors N
5
and N
7
are activated accordingly, so that the signal /CMD applied to the gate of the transistor N
4
and the reference voltage Vref applied to the gate of the transistor N
6
are taken into the receiver circuit RCV. That is, when the signal /CMD is higher in level than the reference voltage Vref, the connection node n
1
between the transistors P
1
and N
1
goes to a low level and the connection node n
2
between the transistors P
2
and N
2
goes to a high level. The node n
1
is connected to the input of the inverter I
1
and the node n
2
is connected to the input of the inverter I
2
. Thus, the output signal D of the inverter I
1
goes low and the output signal /D of the inverter I
2
goes high.
When the signal /CMD is lower in level than the reference voltage Vref, on the other hand, the connection node n
1
goes high, the connection node n
2
goes low, the output signal D goes low, and the output signal /D goes high. When the command latch signal CL is low, the transistors P
3
to P
5
are activated, so that both the connection nodes n
1
and n
2
go high. Thus, the output signals D and /D are both held at a low level.
The receiver circuit RCV holds the state of the signal /CMD only when the command latch signal CL is activated. When the command latch signal CL is activated, a high current flows to sense the signal state at high speed, resulting in a considerable power dissipation.
As described above, in the conventional command receiver shown in
FIG. 4
, the receiver circuits are activated with each cycle of the clock signal to monitor the input signals because it is not known when the command state changes. Therefore, when the number of commands increases and hence the number of signals forming a command increases, the number of receiver circuits RCV that are activated with each cycle of the clock signal increases, and power dissipated by those receiver circuits increases. In addition, when the clock cycle time is reduced with increasing speed of circuit operation, the number of cycles per unit time increases, resulting in a further increase in power dissipation. Furthermore, it is difficult to adjust accurately all the high-speed receiver circuits so that they are equal to one another in setup time and hold time. In the event of differences among the receivers in signal capture time and hold time, wrong commands might be produced.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a clock-synchronous system which permits a plurality of signals to be monitored reliably without increasing power dissipation.
According to an aspect of the present invention, there is provided a clock-synchronous system comprising: a first receiver circuit for capturing an indication signal indicating an input signal capture cycle in synchronization with a clock signal; an activation signal producing circuit responsive to the indication signal for producing an activation signal; and a second receiver circuit responsive to the activation signal for capturing an input signal.
According to another aspect of the present invention, there is provided a clock-synchronous system comprising: a first activation signal producing circuit for producing a first activation signal with each clock of a clock signal; a first receive

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