Clock synchronous serial information receiving apparatus receivi

Details Clock synchronous serial information receiving apparatus receivi Clock synchronous serial information receiving apparatus receivi

1994-06-30

1996-09-24

Heckler, Thomas M.

Excavating

371 379, 364271, 3642711, 364DIG1, G06F 114

Patent

active

055599982

ABSTRACT:
A clock synchronous information receiving apparatus comprising a control signal circuit 6 for receiving a communication clock 3 and outputting a control signal 8, a control signal generating circuit 10 for outputting three control signals 121, 122, 123 differing in the timing of changing from high level to low level in synchronism with the communication clock 3, a communication data compensation circuit 11 for storing communication data 5 at the falling timing of the three control signals 121, 122, 123 of the control signal generating circuit 10, and determining the value of the communication data 5 from the stored values and sending out compensated communication data 50, and a serial/parallel converting circuit 7 for converting the compensated communication data 50 outputted serially from the communication data compensation circuit 11 into parallel and outputting into an 8-bit bus 9, thereby capable of receiving data correctly when noise is generated on the communication data.

REFERENCES:
patent: 3643027 (1972-02-01), Goldberg
patent: 4132975 (1979-01-01), Koike
patent: 4227175 (1980-10-01), Newman
B. P. Lathi, "Modern Digital And Analog Communication Systems", 1989, pp. 192-194 and 196-206.
Joseph D. Greenfield, "Practical Digital Design Using Ics", 1983, pp. 575-578.
Mitsubishi One-Chip Microcomputer M377202S1FP, M37720S1AFP, User's Manual 2-106- 2-147, Jul. 1991.

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