Clock synchronous semiconductor memory device for determining an

Details Clock synchronous semiconductor memory device for determining an Clock synchronous semiconductor memory device for determining an

1997-06-20

1998-11-10

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523008, G11C 800

Patent

active

058354484

ABSTRACT:
A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.

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"Self-Time RAM:STRAM", Chikai OHNO, Fujitsu Sci. Tech, J. 24, 4 (Dec. 1988), pp. 293-300.

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