Clock-synchronous semiconductor memory device and method for acc

Details Clock-synchronous semiconductor memory device and method for acc Clock-synchronous semiconductor memory device and method for acc

1993-03-01

1994-06-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Combined random and sequential addressing

365219, 365221, 365240, G11C 700, G11C 800

Patent

active

053233581

ABSTRACT:
A method for accessing a clock-synchronous semiconductor memory device including memory cells arranged in matrix. The cells are divided into at least two blocks, access to the cells in these blocks is designated from address data provided from an external device, and access to the memory cell is executed synchronously with an externally-supplied clock signal, which comprises setting the other blocks in an access preparation state or in an access operation standby state while one block is in an access operating state, setting a certain block in the access operating state via the access preparation state when the certain block is designated for the access operation by the address data and if the certain block is in the access operating state, and setting a certain block in the access operating state immediately when the certain block is designated for the access operation by the address data and if the certain block is in the access preparation state or in the access operation standby state. In the device, the designation of the cell in the block to be accessed is set using address data designating a block externally-provided from outside of the device.

REFERENCES:
patent: 4891794 (1990-01-01), Hush et al.
patent: 5018110 (1991-05-01), Sugiyama et al.
patent: 5200925 (1993-04-01), Morooka

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