Clock synchronous semiconductor memory device allowing...

Details Clock synchronous semiconductor memory device allowing... Clock synchronous semiconductor memory device allowing...

1998-10-27

2002-12-03

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C365S201000, C365S233100

Reexamination Certificate

active

06489819

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device operating in synchronization with a clock signal and, more specifically, to a clock synchronous semiconductor memory device of which timing margin can be tested by using a clock signal at a lower speed than the clock signal in normal operation mode.
2. Description of the Background Art
In recent years, operation frequency of a microprocessor (MPU) has been improved remarkably. By contrast, improvement in operation frequency of a memory, in particular, of a dynamic random access memory (DRAM) used as a main storage is relatively modest. This results in increased difference in speed of operation between MPU and DRAM, so that data transfer rate between the MPU and the main storage (DRAM) comes to be determined by the speed of operation of the DRAM, hindering high speed data transfer between the MPU and the main storage. Namely, the speed of operation of the DRAM has been a bottleneck against improved performance of the overall system.
Conventionally, in the DRAM, high speed data transfer has been implemented by a high speed operation mode such as a fast page mode or an EDO (Extended Data Output) mode, while band width of data transfer is increased by adopting wide word configuration of ×16 bits, for example, to improve data transfer rate.
However, even if the high speed operation mode is employed, the operation frequency itself is about 66 MHz which is much lower than that of the MPU. Therefore, the conventional DRAM does not have sufficiently high operation frequency to be used as the main storage for the MPU having operation frequency of 100 MHz or 200 MHz. When word configuration is simply widened, the number of data input/output pins increases and package size increases, so that it becomes difficult to provide a small size system and package cost increases.
In order to realize higher data transfer rate, clock synchronous memories operating in synchronization with a clock signal, such as a synchronous DRAM (SDRAM), a DDR (Double Data Rate) DRAM and a Sync Link DRAM (SLDRAM) have been developed as DRAMs having higher operation frequency.
FIG. 1
is a timing chart representing operation of a conventional SDRAM. Referring to
FIG. 1
, waveforms of external signals to an SDRAM having
4
bank configuration and inputting/outputting 16 bits of data DQ
0
to DQ
15
at the time of data writing are depicted as an example. Among
4
banks, one bank is designated by bank address signal bits BA
0
and BA
1
. Address signal bits A
0
to A
11
are used as a row address signal (X), and address signal bits A
0
to A
9
are used as a column address signal (Y). Address signal bit A
10
is utilized as a command instructing auto precharge for automatically returning the inside to precharge state after completion of write/read operation, when a command instructing data write or read is applied. Operation of the SDRAM will be described with reference to
FIG. 1
In cycle #
1
of the clock signal CLK, a chip select signal/CS and a row address strobe signal /RAS are set to the L level, and a column address strobe signal /CAS and a write enable signal /WE are set to the H level. The combination of the states of these external control signals is referred to as an active command ACT, and array activation is designated thereby. When the active command ACT is applied, address signal bits A
0
to A
11
applied at that time are used as the row address signal (X), and row selecting operation takes place in the bank that is designated by bank address signal bits BA
0
and BA
1
. Referring to
FIG. 1
, row selecting operation takes place in bank
0
. By the row selecting operation, the addressed row (word line) is driven to a selected state, and data of memory cells connected to the selected word line are amplified and latched by a sense amplifier.
When chip select signal /CS is at the H level at a rising edge of clock signal CLK, every command is treated as an NOP command, and a new operation mode is not designated. When clock enable signal CKE is at the H level, an internal clock signal is generated in accordance with an external clock signal, and internal circuitry operates. When the clock enable signal CKE is set to the L level, generation of the internal clock signal in the next cycle is stopped, and the internal circuitry holds the state of that cycle in the next cycle.
In clock cycle #
4
, at a rising edge of clock signal CLK, chip select signal /CS, column address strobe signal /CAS and write enable signal (VWE are set to the L level, and row address strobe signal /RAS is set to the H level. The combination of the states of the control signals at this time is referred to as a write command WRITE instructing data writing, and column selecting operation and writing of data to the memory cells on the selected columns are performed. When the write command WRITE is applied, address signal bits A
0
to A
9
applied at that time are used as the column address signal (Y), and column selecting operation takes place. By bank address signal bits BA
0
and BA
1
, the bank in which column selection is to be done is designated (in the example of
FIG. 1
, bank
0
is designated).
In data writing, when a data mask designating signal DQMU/L is at the L level, data D
0
applied in clock cycle #
4
is taken and an internal write data is generated. When the write command is applied, using a column address signal applied simultaneously with the write command as a leading address, column addresses are internally generated in a prescribed sequence, and column selection operation is performed. In clock cycles #
5
, #
6
and #
7
, data D
1
, D
2
and D
3
are taken respectively, internal write data are generated based on the taken data, and written to the selected memory cells in a prescribed sequence.
When data mask designating signal DQMU/L is set to the H level, data writing is masked, and data writing does not take place. The data mask designating signal DQMU/L is a signal of
2
bits, which can mask data writing byte by byte. As address signal bit A
10
is at the L level when the write command is applied, auto precharge operation is not performed. In the auto precharge operation, precharging operation is automatically done internally (the selected array is driven to the inactive state) at the completion of writing or reading of data of burst length.
In clock cycle #
8
, at the rising edge of clock signal CLK, chip select signal /CS, row address strobe signal /RAS and write enable signal /WE are set to the L level, and the column address strobe signal /CAS is set to the H level. At this time, address signal bit A
10
is set to the L level, and bank
0
is designated by the bank address signal bits BA
0
and BA
1
. The combination of the states of the external control signals is referred to as a precharge command PRE, and the designated bank is driven to the inactive state (the selected word line is driven to the non-selected state).
In clock cycle #
11
, the active command ACT is again applied to bank
0
, and row selecting operation takes place in bank
0
.
In data reading, a read command is applied in place of a write command. The read command is applied by setting, at the rising edge of clock signal CLK, chip select signal /CS and column address strobe signal /CAS to the L level and row address strobe signal /RAS and write enable signal /WE to the H level. At the time of data reading, generally, data is externally output after the lapse of a period referred to as CAS latency, after application of the read command. The read data attains to a definite state at the rising edge of clock signal CLK.
As can be seen from
FIG. 1
, as the external control signals are taken at the rising edge of clock signal CLK, what is required is to consider skew of each of the external control signals and the address signals with respect to the clock signal CLK, and it is unnecessary to take skew between control signals into consideration. This allows reduced timing margin, and therefore interna

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