Clock-synchronous semiconductor memory device

Details Clock-synchronous semiconductor memory device Clock-synchronous semiconductor memory device

2006-08-01

2006-08-01

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C365S194000

Reexamination Certificate

active

07085193

ABSTRACT:
A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal after the control signal is asserted. The latency setting circuit configured to set the latency N, and the latency setting circuit including at least one switch which fixes the latency by use of an externally supplied signal.

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