Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2005-05-17
2005-05-17
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230080
Reexamination Certificate
active
06894945
ABSTRACT:
An internal clock generating circuit generates internal clock signals at a double speed of an external clock signal in a test mode. An input/output circuit inputs/outputs data in a DDR mode in accordance with the double-speed internal clock signal. Particularly, an output drive signal CLKO has a frequency twice as high as that of the internal clock signal, and a data strobe signal DQS is generated as a signal having a frequency twice as high as that of an external data strobe signal. In such a manner, a semiconductor memory device which inputs and outputs data in a DDR mode at a speed twice as fast as that of an external clock signal can be achieved.
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Phan Trong
Renesas Technology Corp.
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