Clock synchronous semiconductor memory device

Details Clock synchronous semiconductor memory device Clock synchronous semiconductor memory device

2002-05-09

2004-02-24

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S225700, C365S230080

Reexamination Certificate

active

06697296

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, to a configuration of an input circuit inputting an external signal to produce an internal signal. More particularly, the present invention relates to a configuration of an input circuit of a clock synchronous semiconductor memory device operating in synchronization with a clock signal.
2. Description of the Background Art
In order to interface with an external device, a semiconductor device is internally provided with an input circuit inputting a signal, as an interface circuit. Such a signal input circuit has not only a function of buffering a signal transferred from an external device to perform waveform shaping of the signal, but also a function of converting an amplitude and/or voltage level of the external signal depending on an interface of the external device to a signal corresponding to a signal amplitude of internal circuitry. As such an input circuit, one of input circuits with various configurations is used according to the external interface.
FIG. 25
is a diagram showing a first configuration of a conventional input circuit. In
FIG. 25
, the input circuit includes: a P channel MOS transistor (an insulated gate field effect transistor)PQ
1
connected between a power supply node and an internal node ND
1
, and receiving an external signal EXS at a gate thereof; and an N channel MOS transistor NQ
1
connected between internal node ND
1
and a ground node, and receiving external signal EXS at a gate thereof.
On internal node ND
1
, an internal signal INS is generated through buffering of external signal EXS. A power supply voltage Vdd is applied to the power supply node.
The signal input circuit shown in
FIG. 25
is a CMOS (Complementary MOS) inverter buffer and converts external signal EXS at TTL (Transistor-Transistor-Logic) level to internal signal INS at CMOS level. External signal EXS may be a signal at CMOS level.
In the configuration of the signal input circuit shown in
FIG. 25
, a input logical threshold voltage is determined by a function of a beta (&bgr;) ratio of MOS transistors PQ
1
and NQ
1
and threshold voltages of MOS transistors PQ
1
and NQ
1
. Therefore, by adjusting the input logical threshold voltage, external signal EXS at TTL level can be buffered to generate internal signal INS at CMOS level.
FIG. 26
is a diagram showing a second configuration of a conventional input circuit. In
FIG. 26
, the input circuit includes: a P channel MOS transistor PQ
2
connected between a power supply node and a node ND
2
, and having a gate connected to node ND
2
; a P channel MOS transistor PQ
3
connected between the power supply node and a node ND
3
, and having a gate connected to node ND
2
; an N channel MOS transistor NQ
3
connected between node ND
2
and a ground node, and receiving external signal EMS at a gate thereof; and an N channel MOS transistor NQ
4
connected between node ND
3
and the ground node, and receiving a reference voltage VREF at a gate thereof.
In the input circuit shown in
FIG. 26
, MOS transistors PQ
2
and PQ
3
constitute a current mirror circuit and a current the same in magnitude as a current flowing through MOS transistor PQ
2
flows MOS transistor PQ
3
(where both have the same size). When external signal EXS is higher than reference voltage VREF, a conductance of MOS transistor NQ
3
is made larger than that of MOS transistor NQ
4
and a larger current flows through MOS transistor NQ
3
, compared with a current flowing through MOS transistor NQ
4
. A current discharged through MOS transistor NQ
3
is supplied from MOS transistor PQ
2
. Therefore, the current of the same magnitude as that supplied by MOS transistor PQ
2
is transmitted to MOS transistor NQ
4
through MOS transistor PQ
3
(where both have the same size). Consequently, a voltage level of internal signal INS from node ND
3
goes to H level.
When external signal EXS is lower than reference voltage VREF, to the contrary, a conductance of MOS transistor NQ
4
is made larger than that of MOS transistor NQ
3
, and a drive current of MOS transistor NQ
4
turns larger than that flowing through MOS transistor NQ
3
. Therefore, in this case, MOS transistor NQ
4
discharges a larger current than that supplied from MOS transistor PQ
3
, to drive internal signal INS from node ND
3
to L level.
It should be noted that in the input circuit shown in
FIG. 26
, a constant current source may be provided between a common source of MOS transistors NQ
3
and NQ
4
and the ground node.
In the case of the input circuit shown in
FIG. 26
, when external signal EXS is small in signal amplitude, and changes in a small amplitude with reference voltage VREF being a center, internal signal INS at CMOS level can be generated at high speed according to a logical level of external signal EXS. Specifically, when a signal line transmitting external signal EXS thereon is terminated with a terminating resistance and a signal amplitude of external signal EMS is made small, by use of the input circuit of a differential amplification type shown in
FIG. 26
, internal signal INS at CMOS level can be generated from external signal EXS of a small amplitude reliably.
FIG. 27
is a diagram showing a third configuration of a conventional input circuit. In
FIG. 27
, the input circuit includes: P channel MOS transistors PQ
4
and PQ
5
connected in series between a power supply node and a node ND
4
, and receiving external signal EXS and an internal control signal INCTL at their respective gates; and N channel MOS transistors NQ
4
and NQ
5
connected in parallel between node ND
4
and a ground node with each other, and receiving external gate EXS and internal control signal INCTL at their respective gates.
In the NOR type input circuit shown in
FIG. 27
, when internal control signal INCTL is at H level, P channel MOS transistor PQ
5
is an off state, while N channel MOS transistor NQ
5
is an on state, and internal signal INS is fixed at a ground voltage level.
On the other hand, when internal control signal INCTL goes to L level, N channel MOS transistor NQ
5
enters an off state, P channel MOS transistor PQ
5
enters an on state, and therefore, a CMOS inverter is equivalently formed by MOS transistors PQ
4
and NQ
4
and internal signal INS is generated according external signal EXS.
The input circuit with the configuration shown in
FIG. 27
operates dynamically according to internal control signal INCTL, and a timing at which external signal EXS is taken in is determined by internal control signal INCTL.
The input circuits shown in
FIGS. 25
to
27
are appropriately selected for use in a signal input section of a semiconductor device depending on an interface and application thereof.
It should be noted that for a configuration of a input circuit, other different configurations can be available according to interfaces in use, not limited to the configurations as shown in
FIGS. 25
to
27
. For example, there is available a differential input circuit for an interface through which small amplitude signals are transmitted in the form of complementary signals.
In the event that a configuration of an input circuit is modified according to an individual interface, if a specific input circuit is formed in an individual semiconductor device according to an external interface to be used, such semiconductor devices are to be fabricated that are the same in configuration of internal circuitry and are different in configuration of the respective input circuits. In such a case, layouts have to be individually designed for the respective input circuits, leading to reduced design efficiency. Furthermore, another necessity arises for fabricating semiconductor devices different from each other only in configuration of input circuits in separate fabrication process steps, reducing a fabrication efficiency and in addition, making post-fabrication product management complicated.
Therefore, conventionally, the following process is employed, in which in a master process, input circuits

Affiliated with

Also associated with

Rating

Clock synchronous semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock synchronous semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock synchronous semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3336390