Clock-synchronous semiconductor memory device

Details Clock-synchronous semiconductor memory device Clock-synchronous semiconductor memory device

2001-10-24

2003-01-21

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189011, C365S236000

Reexamination Certificate

active

06510101

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock-synchronous semiconductor memory device and access method thereof which operates synchronously with a basic clock signal, and, in particular, to a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set synchronously with a basic clock signal, and a clock-synchronous semiconductor memory device and access method thereof in which an address for accessing can be set when a high-frequency basic clock signal is used.
2. Description of the Prior Art
The inventors of the present invention have previously proposed a basic method for controlling a memory operation for a semiconductor memory device synchronized with a basic clock signal (Japan Application No. 3-255354).
At that time, several methods were illustrated for controlling a memory access by means of an external control signal, but nothing was disclosed how to set a external control signals synchronously with a basic clock signal and with respect to setting specific timing for an address signal or the like for the external control signals.
Moreover, there is a problem that it is difficult to access data when a high-frequency basic clock signal is used in a conventional a clock-synchronous semiconductor memory device and access method thereof.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor device comprising a memory cell array having memory cells arranged in rows and columns, the memory cells storing data and being selected according to address signals; control section configured to receive a clock signal and a first control signal, and configured to output a plurality of the data in synchronism with the clock signal after the first control signal is asserted, output of the data beginning a number of clock cycles (latency N) of the clock signal (latency N being a positive integer ≧2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output, and a latency setting circuit configured to set the latency N, the latency setting circuit including at least one switch which permanently fixes a latency.


REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4819213 (1989-04-01), Yamaguchi et al.
patent: 4849937 (1989-07-01), Yoshimoto
patent: 4956820 (1990-09-01), Hashimoto
patent: 5054000 (1991-10-01), Miyaji
patent: 5058074 (1991-10-01), Sakamoto
patent: 5142637 (1992-08-01), Harlin et al.
patent: 5148523 (1992-09-01), Harlin et al.
patent: 5148524 (1992-09-01), Harlin et al.
patent: 5235545 (1993-08-01), McLaury
patent: 5268865 (1993-12-01), Takasugi
patent: 5295115 (1994-03-01), Furuya et al.
patent: 5305277 (1994-04-01), Derwin et al.
patent: 5311483 (1994-05-01), Takasugi
patent: 5313437 (1994-05-01), Toda et al.
patent: 5323358 (1994-06-01), Toda et al.
patent: 5341341 (1994-08-01), Fukuzo
patent: 5343438 (1994-08-01), Choi et al.
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5500829 (1996-03-01), Toda et al.
patent: 5587954 (1996-12-01), Vogley et al.
patent: 5587963 (1996-12-01), Toda et al.
patent: 5612925 (1997-03-01), Toda et al.
patent: 5798979 (1998-08-01), Toda et al.
patent: 5818793 (1998-10-01), Toda et al.
patent: 0 211 565 (1987-02-01), None
patent: 0 260 897 (1988-03-01), None
patent: 0 284 985 (1988-10-01), None
patent: 0 315 194 (1989-05-01), None
patent: 62-223891 (1987-10-01), None
patent: 63-272191 (1988-11-01), None
patent: 2-250132 (1990-10-01), None
patent: 5-2873 (1993-01-01), None
patent: 5-120114 (1993-05-01), None
patent: 6-60640 (1994-03-01), None
patent: WO 92/09083 (1992-05-01), None
Ohno, Chikai, “Self-Time RAM: STRAM”,Fujitsu Sci. Tech. J.,24, Dec. 4, 1988, pp. 293-300.
Dunn, E.C. et al., “Single Counter Controlled Buffer”,IBM Technical Disclosure Bulletin,vol. 20, No. 5, Oct. 1977, pp. 1702-1703.

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