Clock-synchronous semiconductor memory device

Details Clock-synchronous semiconductor memory device Clock-synchronous semiconductor memory device

1995-06-01

1998-10-06

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Sync/clocking

365194, 3652257, 365236, G11C 700

Patent

active

058187936

ABSTRACT:
A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O means is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.

REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4819213 (1989-04-01), Yamaguchi et al.
patent: 4849937 (1989-07-01), Yoshimoto
patent: 4956820 (1990-09-01), Hashimoto
patent: 5054000 (1991-10-01), Miyaji
patent: 5058074 (1991-10-01), Sakamoto
patent: 5235545 (1993-08-01), McLaury
patent: 5268865 (1993-12-01), Takasug
patent: 5295115 (1994-03-01), Furuya et al.
patent: 5305277 (1994-04-01), Derwin et al.
patent: 5311483 (1994-05-01), Takasugi
patent: 5313437 (1994-05-01), Toda et al.
patent: 5323358 (1994-06-01), Toda et al.
patent: 5341341 (1994-08-01), Fukuzo
patent: 5343438 (1994-08-01), Choi et al.
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5500829 (1996-03-01), Toda et al.
Ohno, Chikai, "Self-Timed RAM: STRAM", Fujitsu Sci. Tech. J., 24, 4, Dec. 1988, pp. 293-300.
Dunn, E.C. et al., "Single Counter Controlled Buffer", IBM Technical Disclosure Bulletin, vol. 20, No. 5, Oct. 1977, 1702-1703.

Affiliated with

Also associated with

Rating

Clock-synchronous semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock-synchronous semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock-synchronous semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-86665