Clock synchronous semiconductor device having a reduced...

Details Clock synchronous semiconductor device having a reduced... Clock synchronous semiconductor device having a reduced...

2000-10-04

2001-12-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S226000

Reexamination Certificate

active

06333895

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock synchronous semiconductor device, and particularly to a clock synchronous semiconductor device, such as a clock synchronous semiconductor memory device, of which clock access time can be reduced. More particularly, the invention relates to a structure of a data output portion of a clock synchronous semiconductor memory device.
2. Description of the Background Art
FIG. 31
schematically shows a structure of a data output portion of a clock synchronous semiconductor memory device in the prior art. In
FIG. 31
, a clock synchronous semiconductor memory device includes an internal power supply circuit VDC for producing an internal power supply voltage Vint by lowering an external power supply voltage Vex supplied to a power supply node PDE, a memory cell array MA having a plurality of memory cells arranged in rows and columns, a read circuit PAM receiving internal power supply voltage Vint from internal power supply circuit VDC as one operation power supply voltage, for amplifying data of a selected memory cell in memory cell array MA, a clock buffer CB receiving internal power supply voltage Vint as one operation power supply voltage, for buffering an externally applied clock signal CLKe to produce an internal clock signal CLKi, and an output data control circuit ODC for transferring memory cell data read from read circuit PAM onto an internal data bus DBB in synchronization with clock signal CLKi and transmitting the read data to a data output node group QG.
Output data control circuit ODC receives internal power supply voltage Vint supplied from internal power supply circuit VDC, an external power supply voltage Vex supplied from power supply node PDE and an output power supply voltage VDDQ supplied to a power supply node PDD. Output power supply voltage VDDQ is independent of external power supply voltage Vex, and is dedicated to the output buffer. The purpose of supplying external power supply voltage Vex to output data control circuit ODC is to convert an internal read signal, which is at the level of internal power supply voltage Vint and is applied onto internal data bus DBB, into a signal at the level of external power supply voltage Vex for outputting the read data at the level of output power supply voltage VDDQ to data output node group QG. Now, an operation of a clock synchronous semiconductor memory device shown in
FIG. 31
will be briefly described below with reference to a timing chart of FIG.
32
.
In a clock cycle #a, a read command instructing data reading is issued. In accordance with this read command, selection of an addressed memory cell column in memory cell array MA and activation of read circuit PAM are performed under the control of a command control circuit (not shown). When read circuit PAM is activated, the data of the selected memory cell is transmitted onto internal data bus DBB. Output data control circuit ODC is in a latch state when internal clock signal CLKi is at L-level so that data read onto data bus DBB is not transferred in clock cycle #a.
In a clock cycle #b, output data control circuit ODC takes in data on internal data bus DBB and then transfers the data to data output node group QG in synchronization with internal clock signal CLKi.
Data Q read onto data output node group QC is sampled by an external device in synchronization with external clock signal CLKe in a clock cycle #c. Accordingly, the read data is sampled by the external device when two clock cycles elapse after the read command is applied. Clock cycle periods required after application of the read command and before output of valid data is referred to as a “CAS latency” or a “column latency”.
As shown in
FIG. 32
, the data can be transferred to an external device in synchronization with clock signal CLKi. Since the data transfer speed is determined by clock signal CLKi (CLKe), data transfer can be performed in synchronization with a fast clock signal, and therefore fast data transfer can be achieved.
Internal power supply circuit VDC is used for reducing a charge/discharge current of a signal line and therefore a whole power consumption of the semiconductor memory device. With increase in memory capacity, MOS transistors which are the components of the memory device are increasingly miniaturized. For ensuring reliability of miniaturized MOS transistors (insulated gate field effect transistors), the power supply voltage applied to the MOS transistors is lowered. The reliability of the MOS transistor to be ensured specifically includes reliability (breakdown characteristics) of a gate insulating film having a thickness reduced in accordance with miniaturization of the element, and reliability of an immunity to hot carriers caused by a short-channelization of the MOS transistors due to miniaturization of the components (if hot carries generated by a high drain electric field are trapped in a gate insulating film, insulating properties of the gate insulating film will deteriorate).
FIG. 33
shows an example of a structure of an output data control circuit in the prior art.
FIG. 33
shows a structure of a circuit for transferring data of one bit.
In
FIG. 33
, output data control circuit ODC includes a clocked gate
900
activated when internal clock signal CLKi is at H-level, to pass signals on an internal data line pair DB and /DB, an output data latch circuit
902
for latching signals applied from clocked gate
900
onto internal read data lines /RL
4
and RL
4
, an inverter circuit
903
inverting a signal applied from output data latch circuit
902
onto internal read data line RL
5
, and cascaded inverter circuits
904
and
905
of two stages receiving a signal applied from output data latch circuit
902
onto a complementary internal read data line /RL
5
. Each of these clocked gate
900
, output data latch circuit
902
, and inverter circuits
903
,
904
and
905
receives internal power supply voltage Vint as one operation power supply voltage.
Clocked gate
900
includes an NAND circuit G
1
receiving internal clock signal CLKi and a signal on internal data line DB, and an NAND circuit G
2
receiving internal clock signal CLKi and a signal on internal data line /DB. Internal data lines DB and /DB are included in internal data bus DBB shown in
FIG. 31
, and receives complementary data signals from read circuit PAM.
Output data latch circuit
902
includes NAND circuits G
3
and G
4
forming a flip-flop set when the signal on internal read data line /RL
4
is at L-level and reset when the signal on internal read data line RL
4
is at L-level. Output data latch circuit
902
further includes NAND circuits G
5
and G
6
forming a flip-flop reset when the signal on internal read data line /RL
4
is at L-level and set when the signal on internal read data line RL
4
is at L-level. Output data latch circuit
902
inverts the signals that are transferred from clocked gate
900
onto internal read data lines /RL
4
and RL
4
, and latches and transfers the inverted signals onto internal read data lines RL
5
and /RL
5
.
Output data control circuit ODC further includes a level converting circuit
906
for converting an amplitude of the signal on internal read data line RL
5
to a level of external power supply voltage Vex in accordance with the signal on internal read data line RL
5
and the output signal of inverter circuit
903
, and an output buffer
908
for driving a data output node Q in accordance with the signal that is applied from level converting circuit
906
onto an internal read data line /RL
3
P and the signal that is applied from inverter circuit
905
onto an internal read data line /RL
3
N.
Level converting circuit
906
includes a P-channel MOS transistor T
1
connected between an external power supply node and a node N
1
and having a gate connected to a node N
2
, a P-channel MOS transistor T
2
connected between the external power supply node and node N
2
and having a gate connected to node N
1
, an N-channel MOS transistor T
3
connected bet

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