Static information storage and retrieval – Addressing – Sync/clocking
Patent
1998-08-28
1999-11-23
Mai, Son
Static information storage and retrieval
Addressing
Sync/clocking
365201, G11C 800
Patent
active
059912324
ABSTRACT:
A semiconductor integrated circuit device includes an SDRAM module operating in synchronization with a clock signal, a logic circuit transmitting data with the SDRAM module for effecting necessary processing, a direct memory access circuit taking in and transferring an externally applied signal in synchronization with the clock signal corresponding to an operation clock of the SDRAM module, and a selector selecting either the output signal of the logic circuit and the output signal of the direct memory access circuit in accordance with a test mode instructing signal for application to the SDRAM module. A test of a synchronous memory can be performed by externally making fast and direct access to the synchronous memory without an influence of a skew in a signal.
REFERENCES:
patent: 5294750 (1994-03-01), Sakai et al.
patent: 5712584 (1998-01-01), McClure
patent: 5757705 (1998-05-01), Manning
patent: 5910181 (1999-06-01), Hatakenaka et al.
Hayashi Isamu
Mangyo Atsuo
Matsumura Masashi
Yamazaki Akira
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
Mitsubishi Electric Engineering Company Limited
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