Clock synchronous circuit

Details Clock synchronous circuit Clock synchronous circuit

2002-07-02

2004-11-23

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06822922

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-202552, filed Jul. 3, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock synchronous circuit suitable for clock synchronous memories subjected to a synchronous control using a high-speed clock, such as a double data rate (DDR) type DRAM, synchronous DRAM (SDRAM) and double data rate fast cycle RAM (FCRAM).
2. Description of the Related Art
In recent years, in a computer system, clock synchronous memories such as a synchronous DRAM have sometimes been used because of a demand for the raising of a processing speed. For this clock synchronous memory, a clock synchronized with a clock (hereinafter referred to as an “external clock”) for controlling the memory is also used inside the memory.
However, when a deviation (skew) is generated between the clock (hereinafter referred to as an “internal clock) for use in the memory and the external clock because of influences of a receiver (input buffer), an internal circuit of the memory easily causes a malfunction even with a slight deviation particularly in a high-speed operation. Moreover, data outputted from the memory using the internal clock having the deviation from the external clock hinders a high-speed processing even for a controller in which the data is used.
To solve the problem, in recent years, for the memory, a clock synchronous circuit for synchronizing the internal clock with the external clock with a high precision has been disposed in a chip.
For a constitution of the clock synchronous circuit, two types consisting of a periodic type and phase comparison type have heretofore been known. In particular, synchronous traced backward delay (STBD) as a periodic clock synchronous circuit has a high synchronization speed (speed from when power is turned on until synchronization of the external clock with the internal clock is completed) as compared with a phase comparing clock synchronous circuit. Therefore, power-down is frequently performed, and power consumption can be saved.
FIG. 1
shows a block constitution of a conventional periodic clock synchronous circuit.
An external clock EXTCLK is inputted into a receiver (input buffer)
11
having a delay amount Trc. The receiver
11
outputs a clock CLKSTIN which has a skew of Trc with respect to the external clock EXTCLK. The clock CLKSTIN is inputted into a delay monitor
12
having a delay amount Trc+Tdr and a control pulse generating circuit
13
.
The delay monitor
12
outputs a forward pulse FCLIN based on the clock CLKSTIN. The control pulse generating circuit
13
outputs control pulses P, bP based on the clock CLKSTIN. The control pulse generating circuit
13
is constituted, for example, of a circuit shown in FIG.
6
.
The forward pulse FCLIN is given to a delay line for the forward pulse
14
. The delay line for the forward pulse
14
is constituted of N forward delay units
14
-
1
,
14
-
2
, . . .
14
-n, . . .
14
-N connected in series. Additionally, N and n are both positive numbers, and n<N.
Operations of the N forward delay units
14
-
1
,
14
-
2
, . . .
14
-n, . . .
14
-N are controlled in accordance with the control pulses (forward pulse transmission control signals) P, bP. When the N forward delay units
14
-
1
,
14
-
2
, . . .
14
-n, . . .
14
-N are in an operative state (a state in which the forward pulses can be transmitted), each forward delay unit transmits the forward pulse received from the forward delay unit of a previous stage to the forward delay unit of a subsequent stage.
The forward delay unit
14
-n is constituted, for example, of a circuit shown in FIG.
2
.
A state-holding section
15
is disposed adjacent to the forward pulse delay line
14
. N state-holding units
15
-
1
,
15
-
2
, . . .
15
-n, . . .
15
-N are associated with the N forward delay units
14
-
1
,
14
-
2
, . . .
14
-n, . . .
14
-N.
The forward delay unit into which the forward pulse is inputted changes a state (set/reset) of the corresponding state-holding unit. Concretely, all the state-holding units
15
-
1
,
15
-
2
, . . .
15
-n, . . .
15
-N are in a reset (R) state before the forward pulse FCLIN is inputted into the forward pulse delay line
14
. The state-holding unit corresponding to the forward delay unit into which the forward pulse is inputted changes to a set (S) state from the reset (R) state.
The state-holding unit
15
-n is constituted, for example, of a circuit shown in FIG.
3
.
The N state-holding units
15
-
1
,
15
-
2
, . . .
15
-n, . . .
15
-N in the state-holding section
15
are returned to the reset state by the control pulse (state-holding section reset signal) bP. Moreover, a state-holding section initializing circuit
17
outputs an initializing signal bRSINI based on the reset signal RESET, and forcibly initializes the states of the N state-holding units
15
-
1
,
15
-
2
, . . .
15
-n, . . .
15
-N.
The state-holding section initializing circuit
17
is constituted, for example, of a circuit shown in FIG.
4
.
Additionally, the delay monitor
12
, control pulse generating circuit
13
, forward pulse delay line
14
, state-holding section
15
and state-holding section initializing circuit
17
have an object of monitoring a delay time &tgr;−(Trc+Tdr) required for synchronizing the external clock EXTCLK with the internal clock INTCLK, and these will be referred to as a monitor circuit.
The monitor circuit monitors the delay time &tgr;−(Trc+Tdr), whereas a delay line for a backward pulse
16
has an object of accurately copying the delay time &tgr;−(Trc+Tdr) monitored by the monitor circuit.
The backward pulse delay line
16
has an object of accurately copying the delay time &tgr;−(Trc+Tdr), and is therefore a complete copy of the forward pulse delay line
14
. That is, the forward and backward pulse delay lines
14
and
16
are symmetrically disposed with respect to the state-holding section
15
, and completely have the same circuit constitution. Therefore, the STBD of this example is sometimes called a mirror type STBD.
The backward pulse delay line
16
is constituted of N backward delay units
16
-
1
,
16
-
2
, . . .
16
-n, . . .
16
-N connected in series. The backward pulse delay line
16
accurately copies the delay time &tgr;−(Trc+Tdr) based on the states of the N state-holding units
15
-
1
,
15
-
2
, . . .
15
-n, . . .
15
-N in the state-holding section
15
and clock CLKSTIN, and subsequently outputs a clock STCLK.
The backward delay unit
16
-n is constituted, for example, of the circuit shown in FIG.
5
.
The clock STCLK is passed through a driver
18
having a delay amount Tdr, and is then turned into an internal clock INTCLK synchronized with the external clock EXTCLK.
A synchronous operation principle in the STBD will next be described.
Here, similarly as the STBD shown in
FIG. 1
, the n-th stage forward delay unit
14
-n changes the state of the n-th stage state-holding unit
15
-n, and the backward delay unit
16
-(n−1) of an n−1
st
stage operates based on the state of the n-th stage state-holding unit
15
-n.
FIG. 7
is a waveform diagram showing the synchronous operation principle of the STBD.
A case in which the external clock EXTCLK shown in FIG.
7
and having a period &tgr; is inputted into the receiver
11
will be described.
The external clock EXTCLK has a waveform shaped and amplified by the receiver
11
, and is outputted as the clock CLKSTIN. Assuming that the delay time of the receiver
11
is Trc, the clock CLKSTIN is delayed from the external clock EXTCLK by Trc (FIG.
7
).
The clock CLKSTIN outputted from the receiver
11
is inputted into the delay monitor (mimic delay)
12
, control pulse generating circuit
13
, and backward pulse delay line
16
, respectively.
The control pulse generating circuit
13
forms the clock CLKSTIN into a pulse, and g

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