Clock synchronizing system and synchronizing method

Details Clock synchronizing system and synchronizing method Clock synchronizing system and synchronizing method

1998-03-12

2000-09-12

Nuton, My-Trang

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327141, H03L 700

Patent

active

061183172

ABSTRACT:
In the case of sending the sampled clock of transmission coded data together with the coded data and regenerating a clock synchronized with this sampled clock on the receiver side, the drawing-in is speeded up on the received side for the clock information items SCRn sent at unequal intervals. In the case of generating a control voltage of the VCXO in accordance with the received SCRn and the SCCn by the counter, the CPU calculates the amount of frequency fluctuation per unit time and generates a control voltage in accordance with this amount of fluctuation. Thereby, even if SCRn are received at unequal intervals, a rapid follow-up control of the PLL loop including the VCXO becomes possible.

REFERENCES:
patent: 5440259 (1995-08-01), Yokomura
patent: 5572157 (1996-11-01), Takashi et al.
patent: 5574757 (1996-11-01), Ogawa
patent: 5828248 (1998-10-01), Masuda
patent: 5892405 (1999-04-01), Kamikubo et al.

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