Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
2001-08-15
2003-06-03
Le, N. (Department: 2858)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
C327S156000
Reexamination Certificate
active
06573698
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a clock synchronizing method, a clock synchronizing circuit, and a semiconductor device using the clock synchronizing circuit, and more particularly, to a clock synchronizing method, a clock synchronizing circuit, and a semiconductor device using the clock synchronizing circuit which method and circuit adjust the phase of a clock into a predetermined relation to a reference clock.
2. Description of the Related Art
Recently, a semiconductor device has been required to operate in synchronization with a high-speed clock (for example, at hundreds MHz). Therefore, a semiconductor device is preferably provided with such a clock synchronizing circuit as a PLL (Phase Locked Loop) circuit and a DLL (Delay Locked Loop) circuit.
The DLL circuit adjusts the phase of a clock by delaying the clock properly so as to generate a clock having a predetermined phase with respect to a reference clock. A delay circuit that delays the clock has characteristics that a cutoff frequency is decreased and a noise property is deteriorated as the delay time thereof is increased. Consequently, the DLL circuit adjusts the delay time from small to large so as to make the delay time as small as possible.
In controlling a delay circuit like this, in order to generate a clock (hereinafter referred to as a synchronous clock) having a predetermined phase with respect to a reference clock, an advancement or delay of the synchronous clock with respect to a reference clock is detected so as to control the delay time according to the detection result. However, in a case of making the delay time small immediately after the DLL circuit starts to operate, the delay time cannot be adjusted from small to large.
Thereupon, as shown in
FIG. 1
, a conventional DLL circuit adjusts the delay time from small to large by dividing the frequencies of a reference clock and a synchronous clock.
FIG. 1
is a timing diagram as an example explaining operations of the conventional DLL circuit.
FIG.
1
-(A) indicates the reference clock (Ref.CLK). FIG.
1
-(B) indicates the synchronous clock (Int.CLK). Before dividing the frequencies of the reference clock and the synchronous clock, it is not clear which edge in FIG.
1
-(B) corresponds to an edge A in FIG.
1
-(A). Thereupon, in order to clarify the correspondence between an edge of the reference clock and an edge of the synchronous clock, the frequency of the reference clock indicated by FIG.
1
-(A) is divided by 4:2 so as to generate a frequency-divided clock indicated by FIG.
1
-(C), the frequency-divided clock indicated by FIG.
1
-(C) is inverted so as to generate an inverted clock indicated by FIG.
1
-(D), and the frequency of the synchronous clock indicated by FIG.
1
-(B) is divided by 2:2 so as to generate a frequency-divided clock indicated by FIG.
1
-(E).
For example, an edge in FIG.
1
-(D) and an edge in FIG.
1
-(E) found in an ellipse
1
may be adjusted to each other, and the phase of an edge
4
of the synchronous clock indicated by FIG.
1
-(B) is controlled with respect to an edge B of the reference clock indicated by FIG.
1
-(A). In other words, an edge of the synchronous clock is controlled to coincide with an edge of the reference clock N periods behind so that the delay time is adjusted from small to large.
By the way, a DLL circuit is required to operate within a predetermined range of clock periods. For example, when the minimum delay time of a delay circuit is tmin, the maximum delay time thereof is tmax, the minimum period of the reference clock is Tmin, the maximum period thereof is Tmax, and the number of clocks between the edge A and the edge B is N, these values have the following relationships represented by expressions (1) and (2).
N
=mod(
tmin/Tmin
) (1)
tmax>N×Tmax−tmin
(2)
From these expressions, it is understood that the maximum delay time tmax becomes large depending on N. The maximum delay time tmax of the delay circuit becoming large means an increase in the circuit scale, causing a problem of an increased area occupied by the delay circuit and the DLL circuit (a clock synchronizing circuit). On the contrary, since a circuit scale is expected to decrease for the sake of costs, an area occupied by the clock synchronizing circuit has to be restricted as small as possible.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful clock synchronizing method, a clock synchronizing circuit, and a semiconductor device using the clock synchronizing circuit in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a clock synchronizing method, a clock synchronizing circuit, and a semiconductor device using the clock synchronizing circuit which method and circuit can adjust the phase of a clock into a predetermined relation to a reference clock by using a small delay time.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a clock synchronizing method comprising the steps of:
detecting a phase difference of a synchronous clock from a reference clock; and
varying a phase of the synchronous clock in one direction when the phase difference is not within a predetermined range, and varying the phase of the synchronous clock in one of the one direction and the other direction according to the phase difference when the phase difference is within the predetermined range.
Additionally, in the clock synchronizing method according to the present invention, the step of detecting may include:
a first step of judging whether or not the phase difference is within the predetermined range; and
a second step of judging whether the phase of the synchronous clock is ahead of or behind a phase of the reference clock.
Additionally, in the clock synchronizing method according to the present invention, the step of varying may vary the phase of the synchronous clock in a direction that delays the phase of the synchronous clock when the phase difference is within the predetermined range and the phase of the synchronous clock is ahead of a phase of the reference clock, and may vary the phase of the synchronous clock in a direction that advances the phase of the synchronous clock when the phase difference is within the predetermined range and the phase of the synchronous clock is behind the phase of the reference clock.
According to the present invention, by judging whether or not the phase difference of the synchronous clock from the reference clock is within the predetermined range so as to adjust the direction in which to vary the synchronous clock according to the judgment result, the phase of the synchronous clock can be varied in one direction until the phase difference comes within the predetermined range, and the phase of the synchronous clock can be varied in the one direction or the other according to the phase difference after the phase difference comes within the predetermined range. Therefore, the maximum delay time of a delay circuit can be reduced, and accordingly an area occupied by a clock synchronizing circuit can be decreased.
Additionally, in the clock synchronizing method according to the present invention, the step of varying may vary the phase of the synchronous clock at a first time interval in the one direction when the phase difference is not within a predetermined range, and varies the phase of the synchronous clock at a second time interval in one of the one direction and the other direction according to the phase difference when the phase difference is within the predetermined range.
According to the present invention, by differentiating the time interval at which to vary the phase of the synchronous clock depending on whether or not the phase difference of the synchronous clock from the reference clock is within the predetermined range, the time interval at which to vary the phase of the synchronous clock can be made small when the phase di
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
He Amy
Le N.
LandOfFree
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