Clock synchronizing circuit with power save mode

Details Clock synchronizing circuit with power save mode Clock synchronizing circuit with power save mode

1997-11-19

2000-02-29

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327148, 327161, 375374, 375375, H03L 706

Patent

active

060314028

ABSTRACT:
A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predetermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.

REFERENCES:
patent: 4392066 (1983-07-01), Hirao
patent: 4893319 (1990-01-01), Ziuchkovski
patent: 4982110 (1991-01-01), Yokogawa et al.
patent: 5235422 (1993-08-01), Ido et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5789947 (1998-08-01), Sato

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