Clock synchronizing circuit of data transmission system

Details Clock synchronizing circuit of data transmission system Clock synchronizing circuit of data transmission system

1995-08-25

1996-08-27

Chin, Stephen

Pulse or digital communications

Synchronizers

375356, H04L 700

Patent

active

055508740

ABSTRACT:
A clock synchronizing circuit of a data transmission system for synchronizing a serial input data at an input clock with a new system clock at each channel of a receiving station to produce serial output data when transmitting multi-channel data using transmitting lines different from each other in length between data transmission systems distant from each other. This circuit includes a write signal generator for counting the input clock provided from transmitting station to generate write signals of plural bits; enable signal generator for performing a logical AND with the write signals of plural bits generated from the write signal generator to produce a plurality of enable signals; a serial-parallel converter for converting the serial input data into parallel data in response to the plurality of enable signals of the enable signal generator and the input clock; a selecting signal generator for counting the system clock to generate selecting signals of plural bits; a multiplexer for multiplexing the parallel data provided from the serial-parallel converter in response to the selecting signals to produce the serial output data; and D flip-flop for synchronizing the serial output data produced from the multiplexer to the system clock to output the serial output data without glitch.

REFERENCES:
patent: 4056851 (1977-11-01), Hovagimyan et al.
patent: 4823365 (1989-04-01), Loginov
patent: 5051990 (1991-09-01), Kato
patent: 5077761 (1991-12-01), Tokunaga
patent: 5119406 (1992-06-01), Kramer
patent: 5291528 (1994-03-01), Verneer
patent: 5293409 (1994-03-01), Doornenbal et al.
patent: 5446766 (1995-08-01), Wrany

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