Clock synchronizing circuit

Details Clock synchronizing circuit Clock synchronizing circuit

1999-11-15

2003-03-25

Corrielus, Jean (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S371000, C327S141000, C327S291000

Reexamination Certificate

active

06539070

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock synchronizing circuit for generating a clock which is synchronized with an input signal.
DESCRIPTION OF THE PRIOR ART
In a conventional clock synchronizing circuit which deals with a modulation signal yielded according to quadrature modulation, clock phase is obtained by using signal which is sampled in such away that in-phase component and orthogonal component of demodulation base band signal are sampled by a sampler respectively.
FIG. 1
shows such the conventional clock synchronizing circuit. In
FIG. 1
, a sampler
301
implements sampling of in-phase input signal ‘SINI’ using sampling clock ‘SMPCLK’, before outputting as in-phase input sampling signal ‘SISAMP’. Further, sampler
302
implements sampling of orthogonal input signal ‘SINQ’ using sampling clock ‘SMPCLK’, before outputting as orthogonal input sampling signal ‘SQSAMP’. Furthermore, angle detector
109
which inputs thereto these in-phase input sampling signal ‘SISAMP’ and orthogonal input sampling signal ‘SQSAMP’, to obtain “tan−1” (SQSAMP/SISAMP), before finding phase of symbol clock to output as phase signal ‘SP’.
Moreover, a sequencer
303
which inputs thereto a sequence start signal ‘SST’, before outputting an initial phase establishment signal ‘SSETP’. A sampling clock generation circuit
304
which inputs thereto a phase signal ‘SP’ and an initial phase establishment signal ‘SSETP’, before outputting a sampling clock ‘SMPCLK’ undergoing phase control such that the symbol clock is synchronized with both of the in-phase input signal ‘SINI’ and the orthogonal input signal ‘SINQ’ with the initial phase establishment signal ‘SSETP’ as input. According to the operation as above, it is capable of implementing initial phase synchronization of the clock.
However, there is the problem that although such the conventional clock synchronizing circuit is capable of being applied in the case of dealing with modulation signal according to quadrature modulation, such the conventional clock synchronizing circuit is incapable of being applied in the case of use of modulation system of, for instance, ‘FSK’ and so forth except therefor.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problem, to provide a clock synchronizing circuit which enables initial phase synchronization of the clock to be realized even though in the case of modulation system except for quadrature modulation in such a way that it uses cosine/sine output circuit for finding cosine component and sine component of initial phase of the symbol clock with simple constitution.
According to a first aspect of the present invention, in order to achieve the above-mentioned object, there is provided a clock synchronizing circuit which comprises a sampler inputting thereto an input signal and a sampling clock, before outputting sampling signal by sampling the input signal with the condition of ‘N’ times of symbol rate, a sequencer for inputting thereto a symbol clock, a sequence start signal, and the sampling clock, before outputting a sign switching signal, a cosine component integration signal, a sine component integration signal, and an initial phase establishment signal, a cosine/sine output circuit inputting thereto an integration clock, the sampling signal, the sign switching signal, the cosine component integration signal, and the sine component integration, before outputting a cosine signal corresponding to cosine component of an initial phase of the symbol clock and a sine signal corresponding to a sine component of the initial phase of the symbol clock, an angle detector inputting thereto the cosine signal and the sine signal, before obtaining initial phase of the symbol clock, thus outputting it as an initial phase signal, a sampling clock generation circuit inputting thereto the initial phase signal and the initial phase establishment signal, before outputting both of the sampling clock which has fixed phase before initial phase establishment, and which is subjected to phase control in such a way that the symbol clock is synchronized with the input signal at the time of initial phase establishment, and the integration clock, and a frequency divider for dividing the sampling clock into symbol clock with 1/N times frequency in order to input it to the sequencer.
According to a second aspect of the present invention, there is provided a clock synchronizing circuit which comprises a sampler inputting thereto an input signal and a sampling clock, before outputting sampling signal by sampling the input signal with the condition of ‘N’ times of symbol rate, a sequencer for inputting thereto a symbol clock, a sequence start signal, and the sampling clock, before outputting a sign switching signal, a cosine/sine selection signal, and an initial phase establishment signal, a cosine/sine output circuit inputting thereto an integration clock, the sampling signal, the sign switching signal, and the cosine/sine selection signal, before outputting a cosine signal corresponding to cosine component of an initial phase of the symbol clock and a sine signal corresponding to a sine component of the initial phase of the symbol clock, an angle detector inputting thereto the cosine signal and the sine signal, before obtaining initial phase of the symbol clock, thus outputting it as an initial phase signal, a sampling clock generation circuit inputting thereto the initial phase signal and the initial phase establishment signal, before outputting both of the sampling clock which has fixed phase before initial phase establishment, and which is subjected to phase control in such a way that the symbol clock is synchronized with the input signal at the time of initial phase establishment, and the integration clock, and a frequency divider for dividing the sampling clock into symbol clock with 1/N times frequency in order to input it to the sequencer.
According to a third aspect of the present invention, in the first aspect, there is provided a clock synchronizing circuit, wherein the cosine/sine output circuit comprises a sign switching circuit inputting thereto the sampling signal and the sign switching signal, before outputting either the sampling signal or a signal obtained by inverting the sampling signal as switching sampling signal in answer to the sign switching signal, a first integrator inputting thereto the switching sampling signal, the cosine component integration signal, and the integration clock, before outputting signal obtained by integrating the switching sample signal as an integration cosine signal only during period which becomes effective due to the cosine component integration signal, a second integrator inputting thereto the switching sampling signal, the sine component integration signal, and the integration clock, before outputting signal obtained by integrating the switching sampling signal as an integration sine signal only during period which becomes effective due to the sine component integration signal, a first averaging circuit inputting thereto the integration cosine signal, before outputting the cosine signal which is obtained while averaging according to the number of times of integration, and a second averaging circuit inputting thereto the integration sine signal, before outputting the sine signal which is obtained while averaging according to the number of times of integration.
According to a fourth aspect of the present invention, in the second aspect, there is provided a clock synchronizing circuit, wherein the cosine/sine output circuit comprises a sign switching circuit inputting thereto the sampling signal and the sign switching signal, before outputting either the sampling signal or a signal obtained by inverting the sampling signal as switching sampling signal in answer to the sign switching signal, a cosine/sine selection circuit inputting thereto the switching sampling signal, and the cosine/sine selection signal, before outputting the switching sampling signal as a cosine comp

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