Clock synchronizing circuit

Details Clock synchronizing circuit Clock synchronizing circuit

1999-12-02

2001-02-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S148000, C327S161000, C375S373000

Reexamination Certificate

active

06184733

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock synchronizing circuit and, more particularly, to a clock synchronizing circuit capable of reducing power consumption.
2. Background of the Related Art
FIG. 1
is a schematic block of a related clock synchronizing circuit. As illustrated in
FIG. 1
, the related clock synchronizing circuit includes a phase comparator
5
, a charge pump
6
, a phase compensator
2
, and a controller
4
.
The phase comparator
5
compares an external clock input signal with an internal clock signal which is obtained by phase-compensating the external clock signal, and a phase error detecting signal (fast or slow). The charge pump
6
is selectively charged or discharged depending on the phase error detecting signal of the phase comparator
5
, and outputs a charge signal for phase error compensation. The phase compensator
2
compensates the phase error of the external clock signal input through an input buffer
1
using the charge signal from the charge pump
6
. The phase-compensated external clock signal is received by output buffer
3
, which converts the phase-compensated external clock signal to an internal clock signal. The controller
4
controls the phase comparators, the charge pump
6
and the phase comparator.
The phase comparator
5
compares the phase of the external clock signal with the phase of a feedback clock signal derived from the internal clock signal. The phase comparator
5
outputs a high signal if the phase of the external clock signal is faster than the phase of the feedback clock signal. The phase comparator
5
outputs a low signal if the phase of the external clock signal is slower than the phase of the feedback clock signal.
FIG. 2
shows operational waveforms of a related clock phase comparator
5
. Referring to
FIG. 2
, when the external clock signal is low at a time corresponding to a rising edge(RE) of the feedback clock signal, the output of the clock phase comparator
5
becomes low, so that the phase error detecting signal for the input external clock signal becomes slow. When the input external clock input is high at a time corresponding to a RE of the feedback clock signal, the output of the clock phase comparator
5
becomes high, so that the phase error detecting signal for the input external clock signal becomes fast.
As stated above, the related clock synchronizing circuit has several problems. Since the phase comparator
5
of the related clock synchronizing circuit only determines whether the phase of the external clock signal is faster than the phase of the reference clock signal, the phase control system continually compensates the phase of the external clock signal, even when their respective phases are substantially synchronized. This increases unnecessary power consumption. In particular, such unnecessary power consumption is caused during a standby state.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a clock synchronizing circuit that substantially obviates one or more of the problems in the related art. An object of the present invention is to provide a clock synchronizing circuit capable of reducing power consumption.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a clock synchronizing circuit according to the present invention includes a first phase comparator for comparing an external clock signal, which is delayed for a predetermined time, with a feedback clock signal to detect a first phase error and generate a first phase error detecting signal, a second phase comparator for comparing an external clock signal with a feedback clock signal, which is delayed for a predetermined time, to detect a second phase error and generate a second phase error detecting signal, a charge pump for generating a charge and adjusting a magnitude of the charge in accordance with phase error detecting signals from the first and second phase error comparators, a phase compensator for compensating the phase of an external signal clock in accordance with the magnitude of the charge from the charge pump, and a controller for controlling the clock sychronizing circuit or some portion thereof, and switching the clock sychronizing circuit to a power save mode if the phase of the external clock signal is synchronized with the phase of the feedback clock signal by the phase compensator.
The present invention can be achieved in whole or in part by a clock synchronizing circuit comprising: (1) a phase comparator circuit that outputs a first phase error detecting signal based on a time-delayed external clock signal and a feedback clock signal, and a second phase error detecting signal based on an external clock signal and a time-delayed feedback clock signal; and (2) a phase compensator circuit that inputs the external clock signal, compensates the phase of the input external clock signal based on the first and second phase error detecting signals, and outputs a phase-compensated external clock signal.
The present invention can also be achieved in whole or in part by a clock sychronizing circuit comprising: (1) a first phase comparator that determines a first phase difference between a time-delayed external clock signal and a feedback clock signal, and outputs a corresponding first phase error detecting signal; (2) a second phase comparator that determines a second phase difference between an external clock signal and a time-delayed feedback clock signal, and outputs a corresponding second phase error detecting signal; and (3) a phase compensator that inputs the external clock signal, compensates the phase of the input external clock signal based on the first and second phase differences, and outputs a phase-compensated external clock signal.
The present invention can also be achieved in whole or in part by a method of synchronizing a clock, comprising: (1) determining a first phase difference between a time-delayed external clock signal and a feedback clock signal; (2) determining a second phase difference between an external clock signal and a time-delayed feedback clock signal; and (3) compensating a phase of the external clock signal based on the first and second phase differences.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 4392066 (1983-07-01), Hirao
patent: 4893319 (1990-01-01), Ziuchkovski
patent: 4982110 (1991-01-01), Yokogawa et al.
patent: 5235422 (1993-08-01), Ido et al.
patent: 5451894 (1995-09-01), Guo
patent: 5614855 (1997-03-01), Lee et al.
patent: 5789947 (1998-08-01), Sato

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